Minimum Phase Response in Digitally Controlled Boost and Flyback Converters

The article is dedicated to optimizing the digital current control loop of a thyristor converter-driven electric drive, essential for ensuring stable, precise, and reliable operation of electric drives in automated and industrial systems. The primary goal of this research is to develop and enhance the digital current regulator (DCR), which enables the drive system to achieve desired performance, including rapid and stable response to current changes without excessive overshoot or oscillations. Optimization of the current loop improves energy efficiency, enhances dynamic properties, and increases resistance to external disturbances, all of which are critical for modern electric drive systems. The introduction discusses key aspects of digital current loop optimization, specifically dynamic characteristics such as time delays, sampling rate, and bandwidth, which significantly impact the efficiency of digital controllers. Special attention is given to the tuning of proportional-integral (PI) controller parameters, allowing quick and stable response to current changes. The developed model allows preliminary simulation of the current loop’s performance, providing an opportunity to test different configurations before actual implementation. To improve the accuracy and stability of the system, filtering methods are proposed to reduce the impact of high-frequency noise, ensuring the system’s precision and robustness against external interference. Optimization criteria are introduced, including minimizing the integral square error (ISE) and reducing energy consumption, which significantly decreases system losses and increases the energy efficiency of electric drives. In developing the optimized control loop, the following assumptions are considered: 1) the thyristor converter (TC) operates in continuous current mode, 2) the current loop dynamics are studied within a narrow range of TC phase angle changes, and 3) a discrete dynamic TC model is used with averaging of electromotive force (EMF) over the conduction interval. Optimizing the digital current loop addresses several critical tasks, including enhancing control accuracy, reducing overshoot and oscillations, and improving the system’s dynamic response, allowing for reduced delays and a faster reaction to load changes. The optimization results of the digital current regulator (DCR) show reduced energy consumption and significant improvements in control accuracy. The high-speed performance of the digital current loop enables fast transient processes within a single sampling interval of the thyristor converter, which is crucial for systems requiring rapid regulation. Additionally, the digital control loop provides flexibility in control, as it allows for system adjustments to different operating conditions through a software-based approach. The study’s final results demonstrate the potential of digital current loops in modern electric drives. With advances in microprocessor technology, digital regulators enable more complex control algorithms, including adaptive and predictive strategies, which further enhance system efficiency. These approaches are especially relevant for industrial electric drives that require high precision and response speed, making digital current loops a promising solution for contemporary automated control systems.

The empirically developed force control in cases of the robotic polishing and the rehabilitation robots serve as a motivation for the study of the peculiar dynamic behaviour of digital force control. The effect of the sampling times of the digital controllers are studied analytically, and the corresponding stability charts are presented for different gain and mechanical parameters describing also the different sampling frequencies at the force sensors and in the digital control loop. The types of bifurcations are also identified at the stability limits. As one of the practical conclusions, the negative role of differential gain is explained in digital force control.Key wordsforce controlled robotsdifferential gaindelayed oscillator

DC-DC converters are extensively used for switched mode power supplies. Hence, this chapter presents a design, modelling and hardware implementation of a digitally controlled system and its application to DC-DC buck converter being interfaced with Texas Instruments DSP TMS320F2812 controller for voltage control mode. ADC, compensator and digital PWM are the main building blocks that appears in digital controller design. Conventionally, analog controller is popular to get the desired output voltage in DC-DC converters, whereas, digital controllers offer high speed arithmetic and high resolution. Analog PI controller design approach is reviewed and the digital PI controller design is being implemented in this chapter. Digital control has been applied using standard frequency responses with design by emulation approach. Modulation delay in digital control is very critical while designing for fast control loops. Therefore, this chapter also introduces discrete time modelling of synchronous buck converter from practical standpoint considering feedback loop delays. Whereas, this chapter illustrates PI digital controller design methodology, hardware implementation and experimental verification. Experimental results have been taken from a closed loop 18W buck converter. The transient and steady state performance of the converter using PI controller are also presented with appropriate simulation and hardware results.

In order to make BEPC-II to run at a higher energy, the Institute of High Energy Physics undertook an upgrading project. One of the important factors limiting the energy boost is the power and performance of the dipole magnet power supplies; therefore, these four magnet power supplies are developed for the BEPC-II upgrading. The power supplies adopt topologies of thyristor rectifiers to realize a high-power output. In the control unit of each power supply, a digital current closed loop is adopted, and the key components in the feedback loop are thermostatically controlled. In order to improve the performances of the power supplies, analog voltage regulators are added to the inner control loops. These four power supplies have been tested and have already been officially used in BEPC-II, and their powers have reached the requirements of the upgrading. The test results of the current stability are described and shown in this paper, which testifies that the stabilities meet the design parameters. A digital control is applied to each SCR rectifier control. The performances of the power supplies are improved by the combination of digital current control loops and the analog voltage control loops, which makes the performances of the dipole magnet power supplies meet the requirements of the upgrading project.

Abstract. Switched-mode power supplies (SMPS) convert an input DC-voltage into a higher or lower output voltage. In automotive, analog control is mostly used in order to keep the required output voltages constant and resistant to disturbances. The design of robust analog control for SMPS faces parameter variations of integrated and external passive components. Using digital control, parameter variations can be eliminated and the required area for the integrated circuit can be reduced at the same time. Digital control design bears challenges like the prevention of limit cycle oscillations and controller-wind-up. This paper reviews how to prevent these effects. Digital control loops introduce new sources for dead times in the control loop, for example the latency of the analog-to-digital-converter (ADC). Dead times have negative influence on the stability of the control loop, because they lead to phase delays. Consequently, low latency is one of the key requirements for analog-to-digital-converters in digitally controlled SMPS. Exploiting the example of a 500 kHz-buck converter with a crossover frequency of 70 kHz, this paper shows that the 5 µs-latency of a ΔΣ-analog-to-digital-converter leads to a reduction in phase margin of 126°. The latency is less critical for boost converters because of their inherent lower crossover frequencies. Finally, the paper shows a comparison between analog and digital control of SMPS with regard to chip area and test costs.

Controller tuning based on linear small-signal models often results in poor closed-loop bandwidth in a boost converter in which there exists a right-half-plane (RHP) zero. This is because of the fact that small-signal models often ignore fast switching dynamics; thus the performance improvement cannot be fully explored. This paper proposes a geometry tuning in a digitally current mode controlled multiphase boost converter operating under a fixed-frequency digital pulse-width modulator (DPWM) throughout. This achieves proximate time optimal transient recovery for load step transients using a normalized load current feedforward. The latter results in near load invariant regulation; thus, a small integral gain is sufficient for minimizing the steady state error. A GaN-based 4-phase boost converter prototype is made for 48 V rated output voltage, and the measured efficiency is found to be around 97% for the input voltage range of 12 to 36 V. Test results demonstrate nearly a ten fold improvement in the (load) transient response using the proposed tuning over a conventional linear tuning. All the digital controllers are implemented using an FPGA device.

Application of Digital Control Techniques for Satellite Medium Power DC-DC ConvertersThe objective of this paper is to present a work concerning a digital control loop system for satellite medium power DC-DC converters that is done in Space Research Centre. The whole control process of a described power converter is based on a high speed digital signal processing. The paper presents a development of a FPGA digital controller for voltage and current mode stabilization that was implemented using VHDL. The described controllers are based on a classical digital PID controller. The converter used for testing is a 200 kHz, 750W buck converter with 50V/15A output. A high resolution digital PWM approach is presented. Additionally a simple and effective solution of filtering of an analog-to-digital converter output is presented.

Due to the simple structure and low cost, the primary-side-regulation (PSR) flyback converter is widely used in small power applications. As the output voltage is sampled from auxiliary winding in PSR flyback converter, some sampling error exists, especially when continuous conduction mode (CCM) is introduced for higher power. To improve the constant voltage accuracy, a novel digital controlled sampling strategy is proposed. This scheme uses a digital ramp sampling method to sample output voltage in both discontinuous conduction mode (DCM) and CCM, and proposes a voltage adjustment strategy to adjust sampling errors in CCM without weakening the stability in the load-switch process. Finally, the experimental results validate the presented scheme and show that the output voltage error is less than 0.6% in a 20-V, 5-A PSR flyback prototype.

Trajectory prediction control for digital control DC–DC converters with fast transient response

Flyback Converter is an electronic circuit that can increase the output voltage value, the voltage value can be adjusted by changing the value of the duty cycle. This Flyback Converter will be controlled by the Pulse Width Modulation method as the output voltage setting and this research is equipped with a feedback function as monitoring and control of Input Pulse Width Modulation.
 This designed flyback converter aims to provide an isolated power supply as a power source for Brushless Direct Current Motor drivers, and this research was conducted to analyze how much power the flyback converter can produce to be able to supply Brushless Direct Current Motor drivers.
 The results of the analysis obtained in the research Design of flyback converter for power supply of BLDC (Brushless Direct Current) motor driver that is flyback converter is given an input voltage of 31 VDC and output voltage of 15 VDC, rheostat load with a capacity of 39 Ohm, a frequency of 31 KHz in the form of a box wave duty cycle reaches 70%. Flyback converter designed to produce maximum power of 49.6 watts on 70% duty cycle testing.

Dual active bridge (DAB) converters have been gaining increasing popularity in the context of high-frequency solid state transformers. However, modeling of a DAB converter remains a challenge to retain the ripple information for the design of high performance stable digital control under uniform sampling. This paper proposes a discrete-time framework using approximate discrete-time models considering various practical parasitics. These models are used to derive various discrete-time small-signal transfer functions under phase shift modulation using both voltage mode and current mode control techniques. The accuracy of the proposed models is verified through SIMPLIS simulation as well as experimentation in time-domain and in the frequency domain using SIMPLIS simulation. Finally, a design case-study using digital voltage-mode control is considered for a prototype DAB converter under phase-shift modulation with a power rating of 50 W and switching frequency of 500 kHz. The digital controller is implemented using an FPGA device, and the test results are demonstrated. The proposed framework can be extended to different modulation techniques as well as other isolated DC-DC converter topologies to design high frequency digital control.

Primary side regulation (PSR) technology has the characteristics of lower cost and standby power losses. However, there is no algorithm suitable for discontinuous conduction mode (DCM) and continuous conduction mode (CCM) operations of primary side control for flyback converter because of the difficulty in estimating the output voltage correctly. In this paper, a PSR control algorithm suitable for DCM/CCM flyback converter is proposed and implemented with digital micro controller. The voltage drop on the secondary winding and output diode at CCM operation is compensated by sensing the secondary side current at the instant when primary side switch is being turned-on. The secondary side current is zero at the voltage sensing instant and equal to the current at the instant when primary side switch is being turned-on as flyback operated at DCM. In addition, the proposed algorithm can be used to regulate either the output voltage or current very well. An experimental prototype with 150 W rated power is built to verify the feasibility of the proposed control. Experimental results show that the output voltage can be controlled with error less than 0.25%, and the output current error is less than 5%. The conversion efficiency is up to 92.8%.

This paper presents a UPS topology formed by a rectifier, a fly-back converter that serves to keep the batteries charged, two Forward converters operating in parallel lagged by 180° that feed the inverter in the absence of commercial network 260 V and with a full bridge inverter circuit. The resultant power is 1200 W, with a pulse frequency of 25 kHz, the control, signs and protections are implemented in digital form through a digital signal controller (DSC). It presented a comprehensive analysis of the stages of operation and the design procedures for the correct operation of this topology. Simulation results, corresponding to the full functioning of the circuit, are presented to validate the system analysis.

Real Time Analysis of Microprocessor Control System

An integrated digital controller design for dc-dc converter is proposed in this paper. The proposal presents a multiple- band dual-stage (MBDS) delay line A/D converter (ADC) for wide dynamic range of operation with reduced ripple, chip area, and power consumption. This proposal also introduces a novel folding logic for digital error calculation and dual-mode error control PID for improving transient response. A complete closed-loop experimental prototype is demonstrated on a field-programmable-gate- array-based setup. The feasibility and functionality of the proposed digital controller is verified with a closed-loop synchronous buck converter prototype that switches at 1 MHz and regulates over a wide output voltage range of 1.6-3.3 V. The proposed MBDS delay line ADC is fabricated with discrete logic gates and flip-flops. The integrated digital controller is also implemented using standard cell-based design methodology in 0.5-mum CMOS technology. The design reduces 33 % on-chip area compared to an equivalent of 64 tap delay line ADC. The complete digital controller chip takes less than 0.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of silicon area and consumes an average current of 92 muA at 1-MHz switching frequency. The voltage-mode digital loop achieves tracking time of less than 10 mus for 1-V step change of the reference voltage and settling time of 20 mus. Post layout simulation and experimental results are demonstrated.