Trajectory prediction control for digital control DC–DC converters with fast transient response

In this paper, we propose three advanced digital predictive current-mode control (DPCC) algorithms based on a simplified estimation method of duty cycle lost time for asymmetric half-bridge (AHB) LED constant-current driver. They are the digital predictive peak current mode control(DPPCC) algorithm based on leading-edge modulation, the digital predictive quasi-valley current mode control(DPqVCC) algorithm based on trailing-edge modulation, and the digital predictive quasi-average current mode control(DPqACC) algorithm based on double-edge modulation. Simulation and experimental results demonstrate that the three DPCC algorithms can effectively offset the effect of delay on digital control performance, which confirms the superiority of DPqACC. When the DPqACC is applied, the series-load-jump transition times are below 4.5 ms, the maximum load adjustment rate is 0.5%/ V, and the output current can be tuned continuously between 0.3 A and 4.5 A with the longest transition time of 1 ms. Moreover, the three DPCC algorithms are capable of compensating for low-frequency ripples due to the rapid regulation speed of the inner loop. With the electrolytic capacitance removed without additional ripple compensation, the maximum peak-to-peak value of the low-frequency secondary ripple is 0.1163 A (2.91%) when the input is 400 53sin(2ω <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>lin</i></sub> <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i> ) V and the output is 4 A. This approach provides an excellent solution for the digital design of low-ripple AC-DC LED constant-current drivers without electrolytic capacitance.

The point of load (POL) is a power supply, supplies a “low voltage and large current” power to a digital processor application. Digital load current changes very quickly, therefore, a fast transient response is required for POL. In case of the digital controlled POL, “conversion time delay” on the ADC and “internal calculation time” deteriorates its performance. As a result, the output voltage of the Digital controlled POL has a large deviation with the rapid load transient. This is not acceptable for digital processor load. This paper clarifies the delay of the ADC which embedded in the DSP, and the calculation time. We introduce a technique for calculation process improvement, and for shortening the detection delay on the ADC to achieve the high-speed response. The proposed algorithm is verified by using 1/8 brick size of 10 W POL adopting the latest high performance DSP (TMS320F2808: TI), which is newly developed as a commercial product.

This article presents a hysteretic-current-controlled buck converter with constant-frequency-controlled and active-current-sensing (ACS) techniques. This converter used phase-frequency-locked techniques to achieve constant switching frequency. Even if the input voltage or output load current changes, the switching frequency will be as stable as possible at 1 MHz. The proposed ACS circuit will not generate sparks, so the current feedback loop does not need a sample-and-hold circuit, and that will reduce the transient response time. The proposed buck converter has been fabricated with TSMC 0.35 μm CMOS 2P4M technology; the total area of the chip is 1.5 mm × 1.5 mm. The measurement results of this buck converter show that the maximum power efficiency is 90% when the output voltage is 2.5 V and the load current is 300 mA. The output voltage range is 2.5-1 V, and the maximum load current is 600 mA. When the load current varies between 100 and 500 mA, the load transient response is 2.6 μs/2.2 μs and undershoot/overshoot is 20 mV/30 mV. The switching frequency of this buck converter is locked at 1 MHz and the voltage error is within 1%.

This article presents an improved optimum damping current-mode buck converter with fast-transient response and small-transient voltage using new current sensing circuits. The improved optimum-damping circuit, consisting of the dynamic slope generator and the proposed rail-to-rail current sensor, can stabilize the converter during the output current change and can accelerate the transient response to achieve better figure of merit performance. The dynamic slope generator can compensate the slope to prevent subharmonic oscillation issue and lower undershoot/overshoot without an extra slope compensator. The proposed rail-to-rail current sensor increases the input voltage range, accurately captures the inductor current information, and accelerates the transient response as the load current changes, because it eliminates spikes without the need for a sample-and-hold circuit in a conventional current-sensing circuit. The contributions of the proposed converter are listed in the following: 1) we have proposed a new current-sensing circuit without voltage divider, which can be operated rail-to-rail and improve the dynamic response; 2) the new current-sensing circuit consisted of no switches and therefore, without switching noises; 3) the new current-sensing circuit without voltage divider has a smaller chip area and a smaller path delay; 4) the proposed current-sensing circuit needs no sample-and-hold circuits to reduce current spikes; 5) the transient response and transient voltage of the proposed converter are better than others' works; and 6) we have designed and implemented a new optimum-damping current-mode buck converter with better performances compared with previous publications.

Predictive control is an emerging alternative in the control of power converters because of its potential for achieving fast transient response and increased control accuracy. Research on this topic has increased in recent years owing to the availability of high speed digital controllers that can be used for the control of power electronic systems. This study proposes a predictive current control scheme for an improved topology of distribution static compensator (DSTATCOM) intended for load compensation. The proposed strategy derives the converter switching pulses using a cost function that defines the desired system behaviour. An improved DSTATCOM topology employing predictive current control algorithm tracks reference current effectively and makes source current sinusoidal and also in-phase with voltage at the point of common coupling in both steady state and transient conditions. In addition, this scheme does not require any modulation technique. The control scheme has been implemented using field programmable gate array. Simulation and experimentation have been carried out to verify and validate the performance of the proposed scheme and the results are reported in this study.

Design and experimental investigation of digital model predictive current controller for single phase grid integrated photovoltaic systems

In this study, an extended idea has been introduced to improve the dynamic response of single-phase active power factor correction (PFC) converter. A highly non-linear DC-DC converter with inherent parameter uncertainties and the harmful effects due to large disturbance in line voltage are tackled by proposed two sided latched pulse-width-modulation technique with sophisticated feedback system. The effort is made to achieve improvement in the dynamic response of active PFC converter with the primary objective of achieving nearly unity input power factor. The dynamic performance of the proposed converter is analyzed in Power Sim (PSIM) package and is exactly verified with 400 V, 500 W, and 100 kHz laboratory prototype for step change in input voltage and load current.

Single-stage power-factor-corrected AC/DC converters (SSPFC) usually bear high voltage stress on the intermediate storage capacitor due to the lack of control of this voltage. The storage capacitor voltage varies largely with line voltage and load current and is usually higher than the peak line voltage. This paper presents a new single-switch SSPFC based on flyback topology for which the storage capacitor voltage is loosely regulated by the output voltage, reducing the range of storage capacitor voltage fluctuation against change of input voltage and load current. Moreover, the maximum storage capacitor voltage can be smaller than the peak line voltage at high line condition. Without the addition of power switches to increase the control dimension, the proposed converter utilizes a flyback transformer with multiple-output structure to achieve the control purpose. Experimental results verifying the operation of SSPFC are also reported.

This paper presents the design of a digital controller for a 600 W Boundary-Conduction-Mode (BCM) interleaved boost converter used in an ac-dc Power-Factor-Correction (PFC) power supply. The output voltage of a typical boost PFC rectifier contains a 2nd harmonic ripple. Therefore to achieve good power factor, the output voltage compensator must have a low bandwidth, in order to sufficiently attenuate this 2nd harmonic component. As a result, the output voltage can suffer from poor transient response, especially at low input voltage. In this paper, a small-signal model of the output voltage dynamics is derived, where it is shown the open-loop gain of the system decreases with low input voltage. As a result, the output voltage transient response also deteriorates at low levels of input voltage. This can lead to poor voltage transient response for boost PFC converters that are designed to have an operating input line voltage range from 85 to 265 V. Having poor output voltage transient response is undesirable as it can lead to high peak over shoot on the output capacitors, or even worse, lead to an output voltage tracking failure. To correct this behaviour, an adaptive digital voltage compensator is designed to change gain at low input voltage, to ensure the output voltage maintains good transient response. Finally, the derived small-signal analysis, and output voltage compensator performance are experimentally verified on a 600 W interleaved BCM converter.

Servo applications often require fast response inner current loop in order to ensure high dynamic performance of the whole system. Predictive control algorithm can achieve fast dynamic response while avoiding overshoot. However, there is an inherent defect that it relies on the accurate mathematical model of the controlled object. An incremental predictive current control algorithm adopting an improved PWM updating strategy was presented. The relationship between system stability and parameter mismatch was analyzed using root locus method. Simulation and experimental results demonstrate that the proposed incremental predictive current control algorithm shows well dynamic performance and the improved updating strategy achieves significantly increased robustness to parameter mismatch, verifying the feasibility of the methods presented.

Since parabolic current control has fast transient response and high control precision with constant switching frequency, it is an attractive current control strategy for voltage source inverters. The employment of parabolic current control delivers great performance on current waveform control or voltage waveform control. The implementation of parabolic current control usually requires high speed digital-to-analog converters (DACs) to generate a pair of parabolic carriers as the control band. With increases in switching frequency, this requirement becomes more critical because the speed of DAC limits the update rates of the parabolic carriers. This impacts the smoothness and punctuality of the parabolic control band. To solve this issue, a parabolic current control based digital current control strategy is proposed in this paper. The proposed method uses the sensed current of the output inductor to calculate the next duty-cycle. To improve the transient response speed, a duty-cycle adjustment is presented. The performance of the proposed digital control method is verified in simulation.

Multi-cell inverter include an array of singlephase inverters capable of handling higher voltage ratings with lower rating power electronics devices. In this paper, a Real Time Digital Feedback Controller (RTDFBC) combined with a Repetitive Controller is proposed to control a Variable Frequency Drive (VFD) fed by a multi-cell inverter. This digital control is characterized by a very fast transient response, low switching losses, and a proper compensation for load disturbances and cyclical fluctuations.

This paper presents an adaptive threshold voltage (ATV) control to realize a fast transient buck converter. The ATV control can reduce feedback delay, saturate duty cycle, mitigate output transient ripple and suppress output voltage ringing. Thus, the transient response of the buck converter can be enhanced during load current changes while switching frequency of the buck converter can be kept constant at steady state. A prototype converter with the ATV control was designed with 0.35-μm 2P4M CMOS technology. The simulation results demonstrate that the recovery time of the buck converter with the ATV control is less than 3 μs when load current changes between 500 mA and 0 mA.

This paper addresses modeling and control issues related to practical high-frequency digital PWM control of constant-frequency boost, buck-boost and flyback converters. Discrete-time models, including the effects of A/D sampling and delays in the digital control loop, are derived for two cases: output voltage A/D sampling during transistor off time in combination with trailing-edge (TE) DPWM, and A/D sampling during transistor on time in combination with leading-edge (LE) DPWM. We show that off-time sampling with TE-DPWM, which is a common approach in digital controller realizations, can result in desirable minimum-phase responses, thus simplifying compensator design in wide bandwidth closed-loop voltage regulators based on boost or flyback converters. The results are verified by simulation and experimental results on a boost converter prototype.

This paper presents an embedded power management module with adaptive on-chip power processing schemes, tailored for next-generation power-aware VLSI systems. The module comprises a single-inductor multiple-output (SIMO) power converter and a software-defined, digital controller. By using a digital control, the entire converter can be integrated with microprocessor units (MPUs). This enables a hardware-software co-design, where effective power processing carried out at the software level can be directed to generate the most optimal voltages at the hardware level. Such an embedded power management module leads to an integrated and autonomous system-on-chip (SoC) design, which is independent of additional external hardware control. In this design, each power output from the SIMO converter provides a step-up/down voltage conversion, thereby enabling a wide range of variable supply voltage. An adaptive global/local power allocation control algorithm is employed to significantly improve DVS tracking speed and line/load regulation, while the still retaining low cross regulation. Designed with a 180-nm CMOS process, the converter precisely provides three independently variable power outputs from 0.9 to 3.0 V, with a total power range from 33 to 900 mW. A very fast load transient response of 3.25 μs is achieved, in response to a 67.5-mA full-step load current change.