MINOTAuR: A Timing Predictable RISC-V Core Featuring Speculative Execution

Due to the prohibitive cost of worst-case timing analysis for modern processors, the design of time-predictable processors has become increasingly important for hard real-time and safety-critical systems. However, to the best of our knowledge currently there is no effective and widely accepted metric to quantitatively evaluate time predictability of processors, which greatly impedes the advancement of time-predictable processor design. This paper first introduces the concept of architectural time predictability (ATP), which separates timing uncertainty concerns caused by hardware from software. We then propose a metric called Architectural Time-predictability Factor (ATF) to measure architectural time predictability. Our evaluation on a Very Long Instruction Word (VLIW) processor indicates that ATF is an effective metric to quantitatively evaluate architectural time predictability of a whole processor as well as its architectural and microarchitectural components such as caches, branch prediction, speculative execution, parallel pipelines, and Scratch-Pad Memory (SPM). Thus ATF can be used to quantitatively guide architectural design for enhancing time predictability or making better trade-offs between performance and time predictability.

We present MINOTAuR, a timing predictable open source RISC-V core based on the Ariane core [28]. We first modify Ariane in order to make it timing predictable following the approach used to design the SIC processor [12]. We prove that the instruction parallelism in the Ariane core does not prevent from enforcing timing predictability. We further relax restrictions by enabling a limited amount of speculative execution and we are still able to formally prove that the core is timing predictable. Experimental results show that the performance is reduced by only 10% on average compared to the original Ariane core.

A 1.0–5.0GHz tunable low-noise amplifier (LNA) in 65nm is presented, which employs dual feedback common gate (CG) topology to reduce the noise figure (NF) and out-of-band interference. The amplitude-detection-based automatic frequency calibration technique is proposed to overcome the effects of the process variation with little extra cost. The measured average frequency error after the calibration is less than 4.4MHz. The proposed dual feedback CG-LNA achieves the power gain of 19∼26dB. The input matching S11 is −18dB∼-5dB, and the NF is 2.4∼3.8dB. The chip consumes 10.06 mA from one 1.2V power supply, with 0.7mm2 die area consumption.

This article describes how the named data networking (NDN) has recently received a lot of attention as a potential information-centric networking (ICN) architecture for the future Internet. The NDN paradigm has a great potential to efficiently address and solve the current seminal IP-based IoT architecture issues and requirements. NDN can be used with different sets of caching algorithms and caching replacement policies. The authors investigate the most suitable combination of these two features to be implemented in an IoT environment. For this purpose, the authors first reviewed the current research and development progress in ICN, then they conduct a qualitative comparative study of the relevant ICN proposals and discuss the suitability of the NDN as a promising architecture for IoT. Finally, they evaluate the performance of NDN in an IoT environment with different caching algorithms and replacement policies. The obtained results show that the consumer-cache caching algorithm used with the Random Replacement (RR) policy significantly improve NDN content validity in an IoT environment.

SummaryHybrid storage systems that consist of flash‐based solid state drives (SSDs) and traditional disks are now widely used. In hybrid storage systems, there exists a two‐level cache hierarchy that regard dynamic random access memory (DRAM) as the first level cache and SSD as the second level cache for disk storage. However, this two‐level cache hierarchy typically uses independent cache replacement policies for each level, which makes cache resource management inefficient and reduces system performance. In this paper, we propose a novel adaptive multi‐level cache (AMC) replacement algorithm in hybrid storage systems. The AMC algorithm adaptively adjusts cache blocks between DRAM and SSD cache levels using an integrated solution. AMC uses combined selective promote and demote operations to dynamically determine the level in which the blocks are to be cached. In this manner, the AMC algorithm achieves multi‐level cache exclusiveness and makes cache resource management more efficient. By using real‐life storage traces, our evaluation shows the proposed algorithm improves hybrid multi‐level cache performance and also increases the SSD lifetime compared with traditional multi‐level cache replacement algorithms. Copyright © 2015 John Wiley & Sons, Ltd.

We consider the problem of on-chip L2 cache management and replacement policies. We propose a new adaptive cache replacement policy, called Dueling CLOCK (DC), that has several advantages over the Least Recently Used (LRU) cache replacement policy.

In previous research on cache replacement policies, have seen that a block usually becomes dead after some uses. By classifying the dead block and discarding them early, there are various policies have been used but still there are number of problems such as cache pollution, high cache miss rate and cache overhead existed which degrades the system performance. In this paper, a new approach for cache replacement policy has introduced which reduces the cache miss rate and cache overhead by using shared L2 level cache. In terms of less miss rate and good hit rate there is need to deploy effective replacement policies. Cache replacement techniques is one of the crucial design parameter that affects the overall processor performance and also become more important with current growing technological moves in the direction of high associative cache . Keywords: Cache pollution; Cache overhead; Cache miss rate; Cache replacement policy (LRU and LFU); Memory overhead;

Data caching in mobile clients is an important technique to enhance data availability and to improve data access time. Due to cache size limitations, cache replacement policies are used to find a suitable subset of items for eviction from the cache. In this paper, we study the issues of cache replacement for location-dependent data under a geometric location model and we have proposed a new cache replacement policy RAAR (Re-entry probability, Area of valid scope, Age, Rate of Access) by taking into account the spatial and temporal parameters. The experimental evaluations using synthetic datasets show that our replacement policy is effective in improving the system performance in terms of the cache hit ratio of mobile clients.

The cache replacement policy is a crucial phase in caching-based systems that deal with the process of selecting applicable cache contents. In this paper, we propose two novel cache replacement algorithms based on the dataset obtained from a typical wireless femto network. In the first algorithm, called Weighted Least Frequently used with an Adaptive Time Window (WLF-ATW), we aim to make a balance between the network's traffic and the recognition of popular contents. The WLF-ATW algorithm takes the frequency and the recency information of files into account to ascertain the popularity of contents. We suggest another new cache replacement policy namely Fairness Scheduling-based with an Adaptive Time Window (FS-ATW) that is based on fairness scheduling in order to minimize the user's access delay. The novelty of our proposed FS-ATW lies in ranking clients according to their last situations that lead to a further user's experience. The effectiveness of these new algorithms is evaluated from the cache hit ratio, transferred byte volume, user's access delay, user's experience, and load balance. A comprehensive numerical evaluation shows that the performance of the proposed WLF-ATW and FS-ATW algorithms is significantly better than some existing cache replacement strategies.

The technology advance in network has accelerated the development of multimedia applications over the wired and wireless communication. To alleviate network congestion and to reduce latency and workload on multimedia servers, the concept of multimedia proxy has been proposed to cache popular contents. Caching the data objects can relieve the bandwidth demand on the external network, and reduce the average time to load a remote data object to local side. Since the effectiveness of a proxy server depends largely on cache replacement policy, various approaches are proposed in recent years. In this paper, we discuss the cache replacement policy in a multimedia transcoding proxy. Unlike the cache replacement for conventional web objects, to replace some elements with others in the cache of a transcoding proxy, we should further consider the transcoding relationship among the cached items. To maintain the transcoding relationship and to perform cache replacement, we propose in this paper the RESP framework (standing for REplacement with Shortest Path). The RESP framework contains two primary components, i.e., procedure MASP (standing for Minimum Aggregate Cost with Shortest Path) and algorithm EBR (standing for Exchange-Based Replacement). Procedure MASP maintains the transcoding relationship using a shortest path table, whereas algorithm EBR performs cache replacement according to an exchanging strategy. The experimental results show that the RESP framework can approximate the optimal cache replacement with much lower execution time for processing user queries.

A bandwidth and effective hit optimal cache scheme for wireless data access networks with client injected updates

As technology scales down at an exponential rate, leakage power is fast becoming the dominant component of the total power budget. A large share of the total leakage power is dissipated in the cache hierarchy. To reduce cache leakage, individual cache lines can be kept in drowsy mode, a low voltage, low leakage state. Every cache access may then result in dynamic power consumption and performance penalties. A trade-off between the amount of leakage power saved on one hand, and the impact on dynamic power and performance on the other hand must be reachedTo affect this trade-off, we introduce caches in which the power level of cache lines is controlled with the cache replacement policy. In a slumberous cache, cache lines are maintained at different power save modes which we call levels, which depend on their order of replacement priorities.We evaluate the trade-offs in the context of PLRU, a common cache replacement algorithm. We explore various assignments of the tranquility levels to lines and compare overall power and performance impacts. As technology scales down, the dynamic power required to energize slumberous cache lines drops drastically while the leakage power savings remain roughly steady. The performance penalty--in cycles-- remains constant with technology scaling for each scheme we evaluate.

Reliability improvement in private non-uniform cache architecture using two enhanced structures for coherence protocols and replacement policies

Due to the increasing gap between CPU and memory speed, cache performance plays an increasingly critical role in determining the overall performance of microprocessor systems. One of the important factors that a affect cache performance is the cache replacement policy. Despite the importance, current analytical cache performance models ignore the impact of cache replacement policies on cache performance. To the best of our knowledge, this paper is the first to propose an analytical model which predicts the performance of cache replacement policies. The input to our model is a simple circular sequence profiling of each application, which requires very little storage overhead. The output of the model is the predicted miss rates of an application under different replacement policies. The model is based on probability theory and utilizes Markov processes to compute each cache access' miss probability. The model realistic assumptions and relies solely on the statistical properties of the application, without relying on heuristics or rules of thumbs. The model's run time is less than 0.1 seconds, much lower than that of trace simulations. We validate the model by comparing the predicted miss rates of seventeen Spec2000 and NAS benchmark applications against miss rates obtained by detailed execution-driven simulations, across a range of different cache sizes, associativities, and four replacement policies, and show that the model is very accurate. The model's average prediction error is 1.41%,and there are only 14 out of 952 validation points in which the prediction errors are larger than 10%.

By rapid growth of the Internet users and devices, thenumber of servers also increase simultaneously which causes the exponentialincrement of the internet traffic and static data. Handling these huge amountsof user requests and efficiently responding to them require high bandwidthlinks, powerful servers and robust equipment, which despite the availability ofthese requirements getting the full user satisfaction is extremely difficultand a tough challenge. In order to overcome the mentioned problem, the cacheservers are being used as a suitable solution. The performance of web cacheserver directly depends on its replacement policies. Several cache replacementpolicies have been proposed in literature each having varied hit rate (HR) andbyte hit rate (BHR) performances on different networks. The replacement policyproposed in this paper is a dynamic cache replacement policy which trainsitself utilizing previous network logs and by exploiting the data miningclustering algorithm. Once the training step is completed, the proposed policyutilizes the normalization formulas to score each metric of the enquiriesincluding recency, frequency, size and delay. Simulation results showed thatthe proposed policy has the optimum performance on different networks and itnot only improved the performance of web cache server in term of HR and BHR,but also decreases the data retrieval time (Delay Ratio (DR)) of the cacheservers.