Speculative Execution and Timing Predictability in an Open Source RISC-V Core

Due to the prohibitive cost of worst-case timing analysis for modern processors, the design of time-predictable processors has become increasingly important for hard real-time and safety-critical systems. However, to the best of our knowledge currently there is no effective and widely accepted metric to quantitatively evaluate time predictability of processors, which greatly impedes the advancement of time-predictable processor design. This paper first introduces the concept of architectural time predictability (ATP), which separates timing uncertainty concerns caused by hardware from software. We then propose a metric called Architectural Time-predictability Factor (ATF) to measure architectural time predictability. Our evaluation on a Very Long Instruction Word (VLIW) processor indicates that ATF is an effective metric to quantitatively evaluate architectural time predictability of a whole processor as well as its architectural and microarchitectural components such as caches, branch prediction, speculative execution, parallel pipelines, and Scratch-Pad Memory (SPM). Thus ATF can be used to quantitatively guide architectural design for enhancing time predictability or making better trade-offs between performance and time predictability.

International audience

Recently, deep-learning (DL) models have paid a considerable attention to timing prediction in the placement and routing (P&R) flow. As yet, the DL-based prior works are confined to timing prediction at the time-consuming global routing stage, and very few have addressed the timing prediction problem at the placement, i.e., at the pre-route stage. This is because it is not easy to "accurately" predict various timing parameters at the pre-route stage. Moreover, no work has addressed a seamless link of timing prediction at the pre-route stage to the final timing optimization through making use of commercial P&R tools. In this work, we propose a framework called DTOC, to be used at the pre-route stage for this end. Precisely, the framework is composed of two models: (1) a DL-driven arc delay and arc output slew prediction model, performing in two levels: (level-1) predicting net resistance (R), net capacitance (C), and arc length (Len), followed by (level-2) predicting arc delay and arc output slew from the R/C/Len prediction obtained in (level-1); (2) a timing optimization model, which uses the inference outcomes in our DL-driven prediction model to enable the commercial P&R tools to calculate the full path delays, setting update timing margins on paths, so that the P&R tools should use more accurate margins on timing optimization. Experimental results show that, by using our DTOC framework during timing optimization in P&R, we improve the pre-route prediction accuracy on arc delay and arc output slew by 20~26% on average, and improve the WNS, TNS, and the number of timing violation paths by 50~63 % on average.

Harassing and fraud calls have spread like viruses in people's lives, many researchers have proposed some solutions to abnormal phone detection. However, most of these methods are passive detection, cannot give accurate prediction in time. In this work, we worked with operators to obtain a volume of real telecom user data and extract a series of comprehensive features. We propose an integration method of classifiers for abnormal phone detection by applying the machine learning algorithm on the data with unbalance and ‘dirty data’. Especially, we use bootstrap sampling method and voting strategy to reduce the false prediction of classier due to noise data. The experimental result shows the effectiveness of our method in contrast with traditional classification algorithm.

Speculative execution refers to the execution of parts of a computation before the execution of the conditional operations that decide whether it needs to be executed. It has been shown to be a promising technique for eliminating performance bottlenecks imposed by control flow in hardware and software implementations alike. In this paper, we present techniques to incorporate speculative execution in a fine-grained manner into scheduling of control-flow intensive behavioral descriptions. We demonstrate that failing to take into account information such as resource constraints and branch probabilities can lead to significantly sub-optimal performance. We also demonstrate that it may be necessary to speculate simultaneously along multiple paths, subject to resource constraints, in order to minimize the delay overheads incurred when prediction errors occur. Experimental results on several benchmarks show that our speculative scheduling algorithm can result in significant (upto seven-fold) improvements in performance (measured in terms of the average number of clock cycles) as compared to scheduling without speculative execution. Also, the best and worst case execution times for the speculatively performed schedules are the same as or better than the corresponding values for the schedules obtained without speculative execution.

This paper studies the effects of hit ratio on the timing predictability of real-time tasks based on trace driven simulation. The impact on execution times of the variance of the hit ratio for different program runs is studied, covering a wide range of cache sizes and organizations. An analytical expression to quantify the timing predictability is derived, so that timing errors due to variations of the hit ratio con be bounded. Based on this result, we derived the upper bound for the worst-case execution time (WCET) when using caches. Using the WCET bounds, some experimental results are presented on the performance impact on hard real-time systems of different cache sizes and organizations. >

This work describes the development of a transported Livengood-Wu (L-W) integral model for computational fluid dynamics (CFD) simulation to predict auto-ignition and engine knock tendency. The currently employed L-W integral model considers both single-stage and two-stage ignition processes, thus can be generally applied to different fuels such as paraffin, olefin, aromatics and alcohol. The model implementation is first validated in simulations of homogeneous charge compression ignition combustion for three different fuels, showing good accuracy in prediction of auto-ignition timing for fuels with either single-stage or two-stage ignition characteristics. Then, the L-W integral model is coupled with G-equation model to indicate end-gas auto-ignition and knock tendency in CFD simulations of a direct-injection spark-ignition engine. This modeling approach is about 10 times more efficient than the ones that based on detailed chemistry calculation and pressure oscillation analysis. Two fuels with same Research Octane Number (RON) but different octane sensitivity are studied, namely Co-Optima Alkylate and Co-Optima E30. Feed-forward neural network model in conjunction with multi-variable minimization technique is used to generate fuel surrogates with targets of matched RON, octane sensitivity and ethanol content. The CFD model is validated against experimental data in terms of pressure traces and heat release rate for both fuels under a wide range of operating conditions. The knock tendency — indicated by the fuel energy contained in the auto-ignited region — of the two fuels at different load conditions correlates well with the experimental results and the fuel octane sensitivity, implying the current knock modeling approach can capture the octane sensitivity effect and can be applied to further investigation on composition of octane sensitivity.

This work describes the development of a transported Livengood–Wu (L–W) integral model for computational fluid dynamics (CFD) simulation to predict autoignition and engine knock tendency. The currently employed L–W integral model considers both single-stage and two-stage ignition processes, thus can be generally applied to different fuels such as paraffin, olefin, aromatics, and alcohol. The model implementation is first validated in simulations of homogeneous charge compression ignition (HCCI) combustion for three different fuels, showing good accuracy in prediction of autoignition timing for fuels with either single-stage or two-stage ignition characteristics. Then, the L–W integral model is coupled with G-equation model to indicate end-gas autoignition and knock tendency in CFD simulations of a direct-injection spark-ignition engine. This modeling approach is about 10 times more efficient than the ones that based on detailed chemistry calculation and pressure oscillation analysis. Two fuels with same Research Octane Number (RON) but different octane sensitivity are studied, namely, Co-Optima alkylate and Co-Optima E30. Feed-forward neural network model in conjunction with multivariable minimization technique is used to generate fuel surrogates with targets of matched RON, octane sensitivity, and ethanol content. The CFD model is validated against experimental data in terms of pressure traces and heat release rate for both fuels under a wide range of operating conditions. The knock tendency—indicated by the fuel energy contained in the autoignited region—of the two fuels at different load conditions correlates well with the experimental results and the fuel octane sensitivity, implying the current knock modeling approach can capture the octane sensitivity effect and can be applied to further investigation on composition of octane sensitivity.

Optimizing throughput of Seq2Seq model training on the IPU platform for AI-accelerated CFD simulations

Recently,Task switching is an important paradigm for studying executive control.Switching cost refer to the performance differences in task-switch and task-repeat trials.Many issues and problems need further exploration.Theoretically,there is disagreement as to whether switch costs actually represents the task-set reconfiguration or the task-set inertia.Many studies have found that a prolonged preparation time reduces switch costs,which has been attributed to a task set reconfiguration process.However,unlike manipulations of preparation time,other studies have varied the predictability of task sequence and found that the preparation benefit was the same for switches and repetitions.The present study explored the interaction of preparation time and foreknowledge in task switching.In addition,in order to study the effects of preparation time predictability on the task switching,the preparation time(CSI) was manipulated by blocked or randomized within subjects. Two explicit task-cuing experiments were used with the same materials and procedure,preparation times of 150ms and 900ms,and foreknowledge of the full-and the partial-foreknowledge.The full-foreknowledge specified both task transition and task identity.The partial-foreknowledge specified only task transition information.The response-stimulus interval was constant at 800ms,to control the amount of repetition priming from the previous trial.To examine the effect of preparation time predictability on the preparation effects of switch costs,in experiment 1,the preparation time was blocked within subjects,and in experiment 2,the preparation time was randomized within subjects.The RT was measured as the main index. Repeated-measure ANOVA was performed for experiment 1 and 2.The results revealed that:(1) Under the conditions of preparation time predictability and unpredictability,the interaction between the preparation time and the foreknowledge was significant.Under the condition of predictability,the RT of repeat task and switch-to task trials decreased with increasing preparation time,but there are no significant differences in switch-to cost;the RT of switch-away task is affected by preparation time,and switch-away cost advanced with prolonging preparation time.Under the condition of unpredictability,the RT of three types of tasks reduced with rising preparation time,but both of switch-to and switch-away cost went up.(2) Compared to the switch-to task,the RT and switch cost of the switch-away task were longer.(3) Under of the two conditions,there is not the preparation effect.The experimental results suggest that the switch cost may represent the preparation of the new task set and a residual component,and the task switching was not effected by the predictability of the preparation time.

Digital Signal Processors (DSPs) are a family of embedded processors with tight constraints on memory, area, and cost. Many such systems have irregular addressing modes where base-plus-offset mode is not supported. However, they have address generation units (AGUs) that can perform auto-increment/decrement address arithmetic instructions in parallel with the same Load/Store instruction. This can be utilized to reduce the number of explicit address arithmetic instructions to minimize the code size. An effective technique for optimized code generation is offset assignment. This technique reduces the code size by finding an offset assignment that can maximally utilize auto-increment/decrement. In this paper, we present an optimal integer linear programming (ILP) solution to the offset assignment problem with variable coalescing and variable permutation. Experimental results on several benchmarks show the effectiveness of our techniques.

Recently, symbolic execution has gained a significant progress in its techniques and applications. However, in practice, scalability is still a key challenge for symbolic execution. In this paper, we present S2PF, which improves the scalability of Symbolic PathFinder by integrating speculative symbolic execution with the general heuristic search framework. In addition, two optimizations are proposed to improve the speculative symbolic execution in S2PF. Experimental results on six programs show that, S2PF can reduce the solver invocations by 36.4% to 48.7% (with an average of 40.3%), and save the search time by 30.6% to 43.5% (with an average of 35%).

The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-end processors can use elaborate techniques like multiple issue, out-of-order execution, speculative execution, value prediction etc. to tolerate high memory latencies, they are often not viable solutions for embedded processors, due to significant area, power and chip complexity overheads. This paper proposes a hardware-software cooperative approach, called priority-based execution to hide cache miss penalty for embedded processors. The compiler classifies the instructions into low-priority and high-priority instructions. The processor executes the high-priority instructions, but delays the execution of low priority instructions. They are executed on a cache miss to hide the cache miss penalty. We empirically evaluate our proposal on the Intel XScale compiler and microarchitecture. Experimental results on benchmarks from Multimedia, MediaBench, MiBench, and SPEC2000 demonstrate an average 17% performance improvements, hiding 75% cache miss penalty.

Online sequential extreme learning machine with forgetting mechanism

Thread-Level Speculation (TLS) is a hardware/software technique that enables the execution of multiple loop iterations in parallel, even in the presence of some loop-carried dependences. TLS requires hardware mechanisms to support conflict detection, speculative storage, in-order commit of transactions, and transaction roll-back. There is no off-the-shelf processor that provides direct support for TLS. Speculative execution is supported, however, in the form of Hardware Transactional Memory (HTM)—available in recent processors such as the Intel Core and the IBM POWER8. Earlier work has demonstrated that, in the absence of specific TLS support in commodity processors, HTM support can be used to implement TLS. This paper presents a careful evaluation of the implementation of TLS on the HTM extensions available in such machines. This evaluation provides evidence to support several important claims about the performance of TLS over HTM in the Intel Core and the IBM POWER8 architectures. Experimental results reveal that by implementing TLS on top of HTM, speed-ups of up to 3.8\(\times \) can be obtained for some loops.