Model and performance of hot-electron MOS transistors for VLSI

A high-performance NOT logic gate (inverter) was constructed by combining two identical metal-insulator-semiconductor field-effect transistors (MISFETs) made on an individual CdS nanobelt (NB). The MISFETs, which used high-κ HfO2 dielectrics as the top-gate insulator layer, show excellent performance, such as low threshold voltage (∼ −0.1 V), a high on/off ratio (∼108), small subthreshold swing (∼65 mV dec−1) and threshold voltage hysteresis (∼30 mV). The supply voltage for the inverter can be as low as 1 V with a voltage gain as high as 14. When the supply voltage is 7 V, the voltage gain is 72, which is the best reported value, as far as we know, for the inverters based on NB/NW n-channel MISFETs. Besides, the inverter can work in a larger input range with highly stable output voltages. Their high output voltages can make full use of the supply voltages, and their low output voltages can be close to zero. NAND and NOR logic gates have been constructed by assembling three such CdS NB MISFETs, which show high performances as well. The operating principle of the inverter is discussed in detail.

An ultra-thin natural-source-based cellulose derivate is used in a bilayer gate dielectric for organic complementary inverters. Extraordinarily high small-signal gains up to 1600, a very sharp transition region (as low as 40 mV), a full rail-to-rail swing, a balanced noise margin of 92.5%, and “long-time” stability are shown, revealing that these inverters are highly suitable for complex circuit designs. For more than a decade now the research in organic electronics was driven by unique consumer markets demanding for electronic circuits on flexible substrates over large areas and ideally at low cost. Meanwhile, versatile macroelectronic applications with attractive form factors such as flexible displays,1-4 large-area sensor arrays,5-11 e-paper,12, 13 low-cost radio-frequency identification tags,14-18 and bendable microprocessors19 have been realized using organic thin-film transistors (OTFTs) as the essential element. In the majority of these applications OTFTs are integrated either in the form of arrays or as digital logic. The fundamental building block of digital logic is the inverter, a circuit that inverts an input signal. Much work has been devoted in the last five years to design unipolar inverters using p-type-only OTFTs.18-23 Unfortunately, unipolar logic based on single gate OTFTs always suffers from high power consumption and low noise margin coupled with high noise margin variability and therefore impedes the fabrication of complex circuits having hundreds or more logic gates.19, 22, 23 In this context, it stands beyond doubt that the integration of both n-type and p-type transistors in complementary organic-based circuits12 is very advantageous due to a lower power dissipation, higher noise margin, better operational stability, and easier design of the circuit.24-27 To date, several major obstacles complicated the development of organic complementary circuits, which are as follows: i) the lack of n-channel OTFTs with a performance comparable to the p-channel OTFTs, ii) the challenge of device stability (difficulty in fabricating OTFTs with hysteresis-free characteristics), and iii) the difficulty in fabricating sufficiently thin gate dielectrics allowing for low supply voltages. Although many recently reported complementary organic inverters are impressive with respect to their low operation voltages (≤5 V),27-36 high static gains (>100 V/V),25, 28, 30, 32 and large noise margins (>80%),25, 35, 37, 38 only few of those can combine low-voltage operation with high gain and sufficient immunity against electrical noise.39 Moreover, there have been few investigations of the influence of hysteresis and threshold voltage shifts on the inverter characteristics, which typically gives rise to electrical instabilities and performance limitations of those devices.32, 39 The inverter's noise margin is the most critical parameter, since it directly determines the maximum complexity of circuits.22 Particularly, interesting applications of organic electronic circuits are found in analog electronics that allow for the read-out and processing of signals from printed large-area sensors and form an interface to silicon electronics. Examples are analog-to-digital (A/D) converters, operational amplifiers, and comparators, all including several tens of transistors, thus requiring both high gain and a large noise margin to be functional as well as sufficient processability. It is interesting to note that the majority of organic complementary inverters already mentioned24-34, 36-40 relied on pentacene as the p-type semiconductor (14 incidences), fluorinated copper phthalocyanine (6 incidences), or N,N′-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (5 incidences) as the n-type material. On the contrary, the variation in gate dielectric materials that are used is much higher with an emphasis on hybrid dielectric systems. Hybrid systems allow accounting for both a high dielectric breakdown voltage and an engineered interface to the semiconductor. Moreover, the implementation of biodegradable and biocompatible materials represents a new niche in the organic electronics research, aimed to address the issues of cost and toxicity to humans and environment posed by nowadays electronics, a topic that was recently reviewed elsewhere.41-43 Accordingly, we have demonstrated the usage of a novel hybrid and biodegradable high-k gate dielectric material system based on a cellulose derivative for low-voltage complementary organic circuits with exceptional high noise margins.35 Previous work done in our laboratories demonstrated the fabrication feasibility of complex circuits, where the electrode patterning was performed by a self-aligned photolithography technique.44, 45 This process can easily be transferred to an anodized aluminum (Al2O3) + trimethylsilyl cellulose (TMSC) based bilayer system; the respective results will be published soon. To follow on this preliminary work we have developed an extraordinarily well-performing complementary inverter technology based on a hybrid dielectric composed of a bilayer of alumina (Al2O3) and trimethylsilyl cellulose (TMSC) and pentacene or C60 for the p-channel and the n-channel organic semiconductor, respectively. It outperforms any inverter reported so far with respect to the combination of excellent key parameters, such as record DC gain of above 500 V/V, low operation voltage of only 4 V, and large noise margin up to 92.5%. In order to clarify the origin for this high performance, special attention is given to the investigation of the semiconductor–dielectric interface, the semiconductor morphology, the nature of traps, the influence of mobility levels on the inverter performance and its long-term stability. This article is not meant to report new materials and systems, but rather find explanations and present a thorough analysis of the extraordinary performance of the cellulose derivative (TMSC) dielectric and the TMSC to semiconductor interface in organic field-effect transistors and simple inverter circuits. All OTFTs presented in this work have a bottom gate, top contact device architecture, as illustrated in Figure 1a. The transistor fabrication process is described in detail in the Experimental Section. The semiconducting layer is pentacene for p-type and C60 (fullerene) for n-type conduction. For the gate dielectric, an inorganic (Al2O3)–organic (TMSC) bilayer is chosen with 28 and 30 nm layer thickness, respectively. The dielectric properties of both single-layer TMSC films and bilayer Al2O3 + TMSC films, were investigated by current–voltage (I(V)), capacitance–frequency (C(f)), and capacitance–voltage (C(V)) measurements in appropriate capacitor structures with 72 nm insulator layer thickness of pure TMSC and 28 + 30 nm of bilayer film of Al2O3 + TMSC, respectively. In Figure 1b, the I(V) curves of a representative capacitor formed by a single layer cellulose dielectric is shown, whereas in Figure S1a (in the Supporting Information) the curve with bilayer dielectric is displayed. A comparison of I(V) curves of a single layer and bilayer dielectric is displayed in Figure 1c. At an electric field of 3.0 MV cm−1 (equivalent to ≈22 V) a current density on the order of 10−6 A cm−2 is observed for the single-layer TMSC. A breakdown field of 4.5 ± 0.3 MV cm−1 is extracted from eight appropriate capacitor structures. One representative C(V) measurement is displayed in Figure 1d. Its capacitance of about 29 nF cm−2 corresponds to a dielectric constant of εR = 2.4 ± 0.2 at 1 kHz with an excellent stability at frequencies down to 0.5 mHz (virtually flat dielectric constant and low dielectric losses which are indicative of a high purity and negligible amount of mobile ionic species) as illustrated in Figure 1e.46 In comparison, capacitors based on the bilayer dielectric have three orders of magnitude lower leakage currents (≈10−9 A cm−2) at an electric field of 3.0 MV cm−1 corresponding to ≈17.5 V and an effective capacitance of 53 nF cm−2 at 1 kHz (see Figure S1a,b, Supporting Information). As can be derived from Figure S1c (in the Supporting Information) the permittivity of the bilayer dielectric also shows excellent stability over the tested frequency range (1 mHz to 10 kHz). The measured capacitance value of the dielectric is in good agreement with calculations by assuming a permittivity of 9 and a thickness of 28 nm for the Al2O3 layer as well as a measured permittivity of 2.4 ± 0.2 (Figure 1e) and 30 nm thickness for the TMSC layer (see the Experimental Section). In any OTFT with bottom gate architecture the surface properties of the gate dielectric (surface energy, surface roughness) decisively affect the arrangement and growth of small molecule semiconductors. The surface energy of spin-coated TMSC thin films was determined by contact angle measurements. With a water contact angle of 98.5°, TMSC can be regarded as a hydrophobic, low energy surface material with a total surface energy of γ = 24.2 ± 0.6 mN m−1, separable in a small polar component γP = 1.8 ± 0.5 mN m−1 and a dispersive component γD = 22.4 ± 0.1 mN m−1. The average surface roughness, indicated by the root mean square (rms)–roughness values, was found to be only 0.77 ± 0.1 nm by atomic force microscopy (AFM) measurements. On this smooth and low energy TMSC surface, a small-grain growth mode with average grain sizes between 150 and 300 nm for pentacene (shown in Figure 1a) and 50 nm for C60 was observed by AFM measurements. In Figure 2, typical electrical characteristics of OTFTs with either C60 or pentacene as the semiconducting layer are plotted. Both p- and n-type transistors are based on the inorganic–organic bilayer gate dielectric composed of Al2O3 and TMSC. The output characteristics ID(VDS) are displayed in Figure 2a,b, whereas the transfer characteristics ID(VGS) are shown in Figure 2c,d. Both transistor types display very small hysteresis between forward and reverse voltage sweeps. The output characteristics show clear saturation, but for the pentacene-based OTFT a non-linear behavior of the drain current at very low drain voltages is observable (Figure 2b). Such an S-shape of the output curve has been already observed and reported for many different device configurations and has sometimes been attributed to a lateral field dependent contact resistance.47-55 In Table 1, the critical device parameters Von (onset voltage), Vthr (threshold voltage), S (subthreshold swing), μlin (charge carrier mobility in the linear regime), and μsat (charge carrier mobility in the saturation regime) are compiled and averaged over eight devices for each transistor type. On average, C60-based OTFTs show a charge carrier mobility of 0.7 cm2 V−1 s−1 in the saturation regime, a threshold voltage of 1.3 V, and a small subthreshold swing of 305 mV dec−1. Pentacene-based OTFTs have on average a mean threshold voltage of −4.7 V, a very small subthreshold swing of 225 mV dec−1, and a field-effect mobility of 0.22 cm2 V−1 s−1 in the saturation regime. The gate leakage currents are very low and in the range of 10−10 A. The balanced performance of our p- and n-type OTFTs, as well as the fact that both transistor types strictly behave as normally off transistors at zero applied gate voltage is a good base for integrating them in complementary organic inverters. A schematic image of such a complementary inverter circuit is displayed in Figure 3a together with the voltage transfer characteristics (VTCs) of a typical device and the static gain measured for operation voltages of VDD = 4, 5, 6, and 7 V. The inverter exhibits extraordinarily high small-signal gains; for all operation voltages, gains above 500 V/V are measured with a maximum value of about 1000 V/V for VDD = 7 V. The best performing device even has a maximum gain value of 1600 V/V. Moreover, a very sharp transition regime (ΔVin ≤ 40 mV) and a full rail-to-rail swing are observed. The extracted inverter parameters are compiled in Table 2. The switching threshold voltages VM are found to be very close to the ideal value of VDD/2 at all operation voltages with a nearly perfect fit (e.g., VM = 2.04 V at VDD = 4 V). In Figure 3b, the mismatches of the threshold voltages to the ideal values (ΔVM) are plotted as a function of VDD revealing a linear increase of ΔVM with the supply voltage. This means that the asymmetry of the VTCs increase with increasing the operation voltages. Additionally, the noise margins (NM) are plotted in Figure 3b as a function of VDD, illustrating the linear decrease of the NM with increasing operation voltage. Such a behavior reveals the direct correlation between ΔVM and NM and is an indication of the deviation of the VTCs from perfect symmetry. The noise margin is an important figure of merit of an inverter stage and measures the immunity against inevitable transistor parameter variations and electrical noise.56 There are several ways to determine the noise margin of an inverter. One convenient way is called the “maximum equal criterion” (MEC), where the NM is found by the maximum square that fits between inverter transition curve and the mirrored inverter curve as shown in Figure 3c.22, 35 The NM values for all the supplied voltages are listed in Table 2. The noise margin is mainly limited by the steepness of the transition ΔVin and the position of the switching threshold voltage VM (VM = Vin = Vout) as shown in Figure 3c. High and balanced noise margins are found when the ideal condition VM = VDD/2 is met, thus when VM = Vin =VDD/2 = Vout. The inverter in Figure 3c has a NM of 1.79, which is 90% of the maximum theoretical value for a supply voltage of 4 V, determined by the “maximum equal criterion.” Additionally, the “negative slope criteria” reveals a balanced NM of 1.85 V (92.5%) for a supply voltage of 4 V. The OTFTs with pentacene and C60 semiconductor layers (as used in the complementary inverters) were also analyzed with regard to their long-term stability. The dependence of their onset voltage and charge carrier mobility on the time period after preparation is plotted in Figure 4 based on measurements of at least five devices for each transistor type. The error bars display the standard deviations. p- and n-type devices exhibit an onset voltage shift of +1.3 and +0.95 V, respectively, over a period of 45 days. The main part of the shift occurred either after the first or after the second measurement and then the onset voltage shift tended to saturate. It seems that both pentacene- and fullerene-based devices stabilized their electrical properties after few days. Between day 8 and day 45 no significant change in the transfer characteristics was observed. Concerning the subthreshold swing, no significant change was observed over 45 days (S = 215 mV dec−1 (0 days), 210 mV dec−1 (8 days), and 225 mV dec−1 (45 days)) in the pentacene OTFTs, indicating that the interface trap density is stable. On the contrary, after 8 days an increase of the swing was observed for the C60 devices from 305 mV dec−1 (0 days), to 410 mV dec−1 (8 days), to 430 mV dec−1 (45 days). The mean value of the charge carrier mobility of the pentacene OTFTs showed no significant variation over 45 days: 0.22 cm2 V−1 s−1(fresh sample), 0.19 cm2 V−1 s−1 (after 8 days), 0.21 cm2 V−1 s−1 (after 45 days). In contrast, a strong reduction of about one order of magnitude (from 0.7 to 0.06 cm2 V−1 s−1 within the first 8 days and to 0.05 cm2 V−1 s−1 after 45 days) was observed for the fullerene transistors. In order to test the reliability of our OTFT devices we have also performed negative and positive bias stress tests. The bias stress was done 1 day after fabrication, on devices which had been previously measured only once. A reversible negative onset voltage shift of about 400 mV was observed under negative bias of −7.5 V over 21 hours stress (see Figure 5a,b) The main part of the negative voltage shift occurred during the first 2 hours (300 mV) whereas shift saturation was reached after 6 hours. The positive bias stress resulted in a significantly smaller positive onset voltage shift (ca. +100 mV over 4 hours stressing the device). Devices that were stored for seven months in the glovebox showed no bias stress effect at all (i.e., shift of the onset voltage) when their transistor characteristics were measured at regular intervals during the storage period. In order to investigate the “long-time” behavior of complementary inverters, electrical measurements were done after 1, 4, 8, and 45 days of the respective device preparation. Inverters were measured 1 day after device stabilization (see Figure 4a,b). The “long-time” behavior of complementary inverters is shown in Figure 4c,d where the VTC and gain curves are plotted as a function of time. For the lowest VDD of only 4 V, a small shift of the switching threshold voltage was measured: starting from 2.04 V after 1 day to an identical value of 2.17 V after 8 and 45 days, respectively, with a related exceptional high noise margin of 1.79 V (90% of the theoretical maximum) after 1 day and 1.74 V (87%) after 8 and 45 days. It is interesting to note that, after 8 days of storage time, the hysteresis in inverter characteristics was virtually negligible (<100 mV, see Figure 4d) and moreover, repeated measurements did not change the inverter transition, although the gain was somewhat reduced (from 503 (0 days) to 320 (8 days) and 195 (45 days)). The operational stability of the VTC was shown over a period of at least 45 days (Figure 4c for VDD = 4 V). Furthermore, the remarkable long-term stability of these TMSC-based complementary inverters was demonstrated by 16 consecutively recorded inverter curves that are virtually superimposed over one another (Figure 5c). The current–voltage characteristics show that the Al2O3 + TMSC bilayer capacitors have substantially lower leakage currents than the single TMSC layer devices. Due to the roughness of the aluminum bottom electrode with spikes up to 10 nm, the anodization process is a convenient method to reduce the leakage currents for at least three orders of magnitude at an electric field of 3 MV cm−1 as displayed in Figure 1d and make the dielectric layer more robust.57 Another advantage of the anodization step is the substitution of the hydroxide of the native oxide layer. Finally, the subsequent short oxygen plasma treatment (see the Experimental Section) is sufficiently removing all residuals left after the anodization process. This procedure allows for the generation of a pure and trap-reduced dielectric interface to the organic semiconductors, by measurements at low revealing a virtually flat permittivity in the mHz to kHz frequency range and low dielectric losses which both are indicative of a high purity and negligible amount of mobile ionic The generation of this excellent interface is in virtually hysteresis-free characteristics of all the One important that the performance of OTFTs, and in the charge carrier is the of the As shown by several the of the surface energy of the to that of the is one important the growth For a low surface energy material with a smooth surface TMSC, a growth mode is and with a rather high density and small grain sizes are formed (see Figure The high density of grain a significant decrease of the charge carrier since grain as charge On the a better between pentacene on low surface energy materials TMSC with and better reduce the of trap thus the mobility of charge in the In there is an between grain related and interface with regard to their influence on charge carrier The low subthreshold swing observed in all our pentacene-based OTFTs is indicative of a low interface trap density which the influence of the large grain trap density on the charge carrier Accordingly, a mobility 0.2 cm2 V−1 s−1 is observed in the p-type devices. In C60 films, the influence of on the charge carrier mobility is by far not as significant as in pentacene films, which is attributed to the of the fullerene In the pentacene OTFTs (see Figure a non-linear current increase in the linear regime of the ID(VDS) output characteristics is at higher gate have been in to such a which can be observed in bottom gate The explanations i) the of the charge carrier mobility for semiconductor ii) currents that the of the mobile by an effective under the drain and iii) large at the electrode from an energy between the work of contact material and semiconductor films, a gate or large contact are found in our of these it has been shown that a mobility in combination with a small contact in a non-linear drain voltage dependence of the current due to The from a of from trap and a dependence of on the drain A respective of the pentacene output curve in Figure the dependence in the regime 2 V, thus indicating that a mobility has to be The of any hysteresis in the I(V) curves and the low and value of the subthreshold swing a low density of interface in the pentacene are not for the observed and the of the as by the of the pentacene layer gives rise to which to a field dependence of the charge carrier This is all the more given that the pentacene grain sizes are 300 nm at a large density of grain As by Figure 4 the characteristics of both pentacene- and C60-based OTFTs show a positive onset voltage shifts storage which after a of measurements. The virtually subthreshold swing in pentacene as well as the negligible hysteresis as the origin of the On the contrary, it seems that trap are for the positive onset voltage shift in are either over time or during the first measurements by the applied positive gate be easily by the gate bias and therefore are not to the swing, but the small onset voltage in pentacene-based It has been reported by many that the of the of trap in pentacene trap also be due to such as at the a at the or a at the fabrication and transfer from the to the measurement stage the semiconductor layer and rise to such For oxygen can even the devices are to but transferred directly and measured in a glovebox with reduced oxygen and water have also observed that the of oxygen with pentacene is in the that these are under device operation with the of oxygen in the grain observed that the storage of devices in and their subsequent measurement in did not a change in their I(V) also observed that the storage time to the first measurement has influence on the device (i.e., on the onset voltage in this of and the first measurement the of to the of oxygen or with the which in a second are by Moreover, also are are not as in the as the (see and This an for the positive shift of the onset voltage between first and second measurement (Figure and also for the saturation of the onset voltage shift in In order to clarify which of are present in our we performed measurements on pentacene films (in and after storage in for (see Figure Supporting Information). storage under a small increase of the at energy is observed that can be attributed to the to and The analysis reveals an increase of the from 0.2 to At the position no change is that trap in our devices for bias stress and the positive onset voltage can mainly be attributed to It be that the of any mobility in pentacene OTFTs against an of pentacene both are to oxygen For the C60 transistors, one a strong decrease of the charge carrier mobility during 8 days of storage which is by all over the device grain This is a effect of The decrease in charge carrier mobility and the at the interface that the subthreshold swing is in a positive onset voltage shift of the C60 transistors. With respect to the complementary inverters, noise margin values beyond from the maximum theoretical value for all supply voltages are and the high operational of the OTFT devices. At a very low supply voltage of 4 V, our bilayer organic complementary inverters have a static gain of more than 500 V/V with a noise margin of 92.5%, which is already reported devices with architecture (see the of inverter performance given in 38 and also gain values above 1000 V/V values up to 1600 were measured for our devices. This is all the most as the charge carrier mobility values of the transistors are not thus the that the of the mobility values between p- and n-channel with the virtually hysteresis are the factors for high gain and high noise margin Accordingly, a mobility 1 be the the is not high ≤ it can be by and p-channel transistors with different In our the mobility is The static of a complementary inverter is determined by technology parameters, the parameters of p- and n-type transistors. A good of these parameters a good saturation of both output can to a significant increase of the gain A is shown in the Supporting Furthermore, high gain values are also determined by the interface An insulator with an low trap density (as this is the for is in having I(V) curves with virtually zero Accordingly, it is to measurements with a very high voltage small voltage thus one to the high gain value of the complementary inverter it by hysteresis The noise margin with increasing VDD due to their strong this is also for the of the VTCs by see Figure A for this behavior can be found in the bias stress that was observed for both types of transistors. The negative shift of Von under negative gate and the positive

A method to implement quaternary circuits using NMOS devices is proposed. The authors have designed a simplified elementary form of inverter and have implemented a series of fundamental logic and memory circuits. These circuits comprise MOS transistors with three values of enhancement-mode threshold voltage and one depletion-mode threshold voltage. The features of these circuits are a small number of MOS transistors, a simple structure, and an exact transfer characteristic. Several fundamental circuits such as inverter, NAND, NOR, and delta literal have been fabricated by conventional NMOS technology. Comparisons between the measured and calculated results indicate a good agreement, taking into account some back-bias effect. The performance of the inverter, including speed, noise margin, and pattern area, is also discussed.

This paper explains our investigation of the effect on 32 nm PMOS device threshold voltage (VTH) by four process parameters, namely HALO implantation, Source/Drain (S/D) implantation dose, compensation implantations, and silicide annealing time. Taguchi method determines the setting of process parameters in experimental design while analysis of variance (ANOVA) determines the influence of the main process parameters on threshold voltage. The fabrication processes of the transistor were performed by ATHENA fabrication simulator, while the electrical characterization of the device was done by an ATLAS characterization simulator. These two simulators were combined and the results were analyzed by Taguchi’s method in order to aid in design and optimizing process parameters. Threshold voltage (Vth) results were used as the evaluation parameters. The results show that the VTH value of –0.10319 V is achieved for a 32 nm PMOS transistor. In conclusion, by utilizing Taguchi’s method to analyze the effect of process parameters, we can adjust threshold voltage (VTH) for PMOS to a stable value of –0.10319 V that is wellwithin ITRS prediction for a 32 nm PMOS transistor. Key words: 32 nm PMOS device, HALO, compensation implantation, S/D implantation,threshold voltage, Taguchi’s method.

A high-throughput on-chip monitoring circuit with a digital output is proposed for the variations of the NMOS and PMOS threshold voltages. A voltage-controlled delay line (VCDL) and a time-to-digital converter (TDC) are used to convert a small difference in analog voltage into a large difference in time delay. This circuit was applied to the transistors of W = 10µm and L = 0.18µm in a 16 × 16 array matrix fabricated with a 0.18-µm process. The measurement of the threshold voltage shows that the maximum peak-to-peak intra-chip variation of NMOS and PMOS transistors are about 31.7mV and 32.2mV, respectively, for the temperature range from −25°C to 75°C. The voltage resolutions of NMOS and PMOS transistors are measured to be 1.10mV/bit and 3.53mV/bit at 25°C, respectively. The 8-bit digital code is generated for the threshold voltage of a transistor in every 125ns, which corresponds to the 8-MHz throughput.

For first time, we report a novel deep sub-micron fully-depleted silicon-on-insulator metal–oxide–semiconductor field-effect-transistor (FD SOI MOSFET) where the channel layer consists of two sections with a step doping (SD) region in order to increase performance and reliability of the device. This new structure that called SD FD SOI structure (SDFD-SOI MOSFET), were used for reaching suitable threshold voltage upon device scaling and reliability improvement. We demonstrate that the electric field was modified in the channel and common peak near the source junction have been reduced in the SDFD-SOI structure. The device demonstrates large enhancements in performance areas such as current drive capability, output resistance, hot-carrier reliability and threshold voltage roll-off. It was found that the device performance is very much dependent upon the SD region parameters. Simulation results show that the proposed structure improved on/off current ratio, and saturated output characteristics compared with conventional SOI structure (C-SOI MOSFET). Also, it was shown that substrate current of SDFD-SOI MOSFET is much lower than the C-SOI MOSFET which presented the lower hot-carrier degradation in proposed MOSFET. Results show that the most short-channel problems in very large scale integrated circuits (VLSI) could be solved and the proposed SDFD-SOI MOSFETs can work very well in deep sub-micron and nanoscale regime.

The original shift-and-ratio method tends to significantly over-estimate the effective channel length Leff of metal–oxide–silicon (MOS) transistors with halo/pocket implants because the carrier mobility of the short transistor tends to be smaller than that of the long transistor. A modification of the original method has been tested on both n-channel metal–oxide–silicon (NMOS) and p-channel metal–oxide–silicon (PMOS) transistors fabricated by state-of-the-art complementary metal–oxide–silicon (CMOS) technology. The values of Leff generated by this method are more reasonable than the original shift-and-ratio method with much less computation time involved. The theoretical basis of our method is that the carrier mobility of the short transistor is approximately equal to that of the long transistor when the gate voltage is close to the threshold voltage for state-of-the-art MOS transistors with <2 nm gate oxide.

Cryogenic temperature dependence of the voltage transfer characteristics of CMOS inverters

4H silicon carbide (4H-SiC) metal-insulator- semiconductor field-effect transistors (MISFETs) with 4H aluminum nitride (4H-AlN) gate insulators have been demonstrated. The 4H-AlN layers are isopolytypically grown on 4H-SiC (1120) by molecular-beam epitaxy. Gate controlled transistor operation was realized using the AlN/SiC MISFETs. The MISFETs exhibit a low gate leakage current (<;10-10 A) and normally ON characteristics with a threshold voltage of approximately -10 V and a field-effect mobility of 0.5 cm2V-1s-1. Capacitance-voltage measurements of AlN/SiC MIS capacitors reveal a large negative flat band shift of -10.9 V, which is consistent with the normally ON characteristics.

A technique to utilize GaAs insulated gate field effect transistors (IGFEI's) with large surface state densities in digital integrated circuits is described. In this technique, the threshold voltage is electrically set to obtain enhancement-mode characteristics of the IGFET's. Due to change in surface charge with time, these circuits will not function at very low frequencies. Several advantages of this IGFET technology over other enhancement-mode GaAs technologies are presented.

A numerical two dimmensional simulation has been used to demonstrate the effect of IGFET channel width on threshold voltage. The computed results agree well with experiments and are used to build an understanding of the mechanism. Potential, field and carrier concentration distributions are used to provide a picture of the geometric interactions.

Analog circuits based on the subthreshold operation of CMOS devices are very attractive for ultralow power, high gain, and moderate frequency applications. In this paper, the analog performance of 100 nm dual-material gate (DMG) CMOS devices in the subthreshold regime of operation is reported for the first time. The analog performance parameters, namely drain-current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> ), transconductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ), transconductance generation factor (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> ), early voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">A</sub> ), output resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sub> ) and intrinsic gain for the DMG n-MOS devices, and and for the DMG p-MOS devices are systematically investigated with the help of extensive device simulations. The effects of different capacitances on the unity-gain frequency are also studied. The DMG CMOS devices are found to have significantly better performance as compared to their single-material gate (SMG) counterpart. More than 70% improvement in the voltage gain is observed for the CMOS amplifiers when dual-material gates, instead of single-material gates, are used in both the n- and p-channel devices.

Both n-channel and p-channel high mobility (Al,Ga)As/GaAs heterostructure insulated gate field effect transistors (HIGFETs) have been fabricated for the first time on the same planar wafer surface using MBE and a self-aligned gate by ion implantation process. Enhancement-mode (E-mode) n-channel HIGFETs have demonstrated extrinsic transconductances of 385 mS/mm at 77 K and 218 mS/mm at room temperature. E-mode p-channel HIGFETs have demonstrated extrinsic transconductances of 59 mS/mm at 77 K and 28 mS/mm at room temperature. These are the highest transconductance values ever reported for a p-channel FET device. The hole field effect mobility was deduced from 3-µm gate length p-channel HIGFETs to be 1,300 cm2/Vs and 500 cm2/Vs at 77 K and room temperature, respectively. The HIGFET approach appears to be very promising for the development of a new generation of high speed, low power complementary circuits.

Because of the application of field-effect transistors, and integrated circuits in space electronic systems and the fact that proton irradiation data at energies typical of a space environment are not extensive, an experimental evaluation of these devices has been conducted. Thee important electrical parameters of these devices were measured before, during, and after irradiation at the Oak Ridge National Laboratory's 22-Mev Cyclotron. The results obtained from the MOS field-effect study show that their degradation processes include that of charge storage in the silicon dioxide insulating layer and radiation-induced changes in surface states. MOS transistors have been found to degrade at orders of magnitude less integrated proton flux than many bipolar and junction field-effect transistors; therefore, for space applications in radiation fields such as Van Allen Belts and solar particle events, these devices may be subject to serious radiation damage. The junction field-effect transistor desplays a large initial spread in device irradiation response. However, it appears to possess a high degree of resistance to proton irradiation. The integrated circuits tested were of the monolithic type and under proton irradiation displayed a large reduction of minority carrier lifetime in the base region of the circuit transistors. Other less important defects are reduction of free carrier concentration and reduction in mobility. Important electrical parameters that are affected by radiation are imput threshold voltages, output low level voltages, leakages currents, and transient characteristics. In conclusion, MOS field-effect transistors and integrated circuits display significant damage characteristics when subjected to a space proton environment.

Intrinsic and generated bulk defects in the gate insulator of silicon insulated gate field effect transistors were examined using a continuous forward-bias pulsed injection technique to inject up to 1017 e/cm2 at 293 and 100 K, for insulator thicknesses ranging between 5.4 and 50.5 nm. The amount of trapping observed at 100 K was about 30 times greater than that at 293 K. The additional trapping at the reduced temperature was determined to come from two sources. One is trapping by existing shallow bulk defects, and the other is an increase in the density of generated bulk defects. The defect generation process is thought to be related to the neutral hole trap becoming unstable during injection, acting as an electron trap. This instability appears to be enhanced as the temperature is reduced to 100 K by a “freeze out’’ effect, or by higher energy carriers that result from a reduction in the thermal scattering. The defect generation rate follows a power law, much like a chemical rate equation, i.e., the rate of defect generation is dependent on the injection current density, much like a chemical reaction is dependent on pressure of the reactive species. The charge centroid of the generated defects, measured from the substrate/oxide interface, was determined at both temperatures and the centroid of the shallow electron traps was determined at 100 K. These were found to be in the range of 6–8 nm at 100 K and 10–16 nm at 293 K. Also, a defect free, or tunneling, region of 2–4 nm extent was determined to exist at each interface. This implies that when the oxide thickness decreases to about 4–8 nm, no threshold voltage shift should result from carrier injection at room, or low temperature, and in fact this behavior was observed in these devices (at least up to 1017 e/cm2 injected). It was found that the shallow traps can be rapidly depopulated by subjecting the devices to ordinary white light during normal device use, pointing to a possible method to improve device reliability at 100 K.