Narrow channel effects in insulated gate field effect transistors

The authors describe a new narrow channel effect by quantum mechanical effects in ultra-narrow MOSFET's. Threshold voltage increase is observed at room temperature in ultra-narrow MOSFET's whose channel width is less than 10 nm. This result is in excellent agreement with simulation that takes account of quantum confinement in the silicon narrow channel, indicating that the increase in threshold voltage is caused by the quantum mechanical narrow channel effect.

In this paper, we present the gamma-radiation induced degradation of the electrical characteristics of N-channel Metal Oxide Semiconductor Field Effect Transistors (NMOSFETs). The exposure was done with a 60Co gamma-ray source over the total dose range of 1 kGy to 10 kGy, with a dose rate of 3.9 kGyhr. The effects of irradiation induced degradation on device parameters such as threshold voltage, low field mobility, device transconductance (Gm), saturation drain current, off state leakage current and subthreshold swing were investigated. The threshold voltage was determined using the linear extrapolation method. The device dimensions with Wide/Long channel that excluded the Narrow Channel Effect (NCE) and the Short Channel Effect (SCE) were measured. The results showed that the threshold voltage, device transconductance and low field mobility decreased but the saturation drain current, off state leakage current and subthreshold swing increased as the gamma irradiation increased. Finally, the macro parameter models were investigated and discussed.

In this paper, we present on the cryogenic characterization of short channel 28-nm FD-SOI nMOS and pMOS transistors having widths of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1 ~\mu \text{m}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.08 ~\mu \text{m}$ </tex-math></inline-formula> at temperatures ranging from T = 300 K down to T = 10 K. We report, for the first time, the alarming concerns that the narrow-width effect imposes on the overall performance of highly scaled FD-SOI technologies, at temperatures below T = 77 K. The performance comparison between nMOS and pMOS devices is based on their drain current, threshold voltage, transconductance, subthreshold slope, low field mobility and total resistance. Our results show that the sensitivity of narrow width effects towards drain current, threshold voltage and total resistance is smaller in pMOS as compared to nMOS. The effective improvement in transconductance is also significantly larger in narrow width pMOS in comparison to their nMOS counterparts. A substantial degradation of subthreshold swing, total resistance and low field mobility is also observed in narrow nMOS devices, which questions the width scaling benefits of these technologies at cryogenic temperatures.

An interactive program has been developed for the graphic generation and the solution of two-dimensional impurity, carrier, potential, and field distributions in small-geometry MOS transistor configurations. Emphasis is placed on conversational operation and three-dimensional display on a graphics terminal with a generation rate, for any self-consistent two-dimensional solution, of less than few minutes for each computation and drawing. Although this limited the approach to a solution of the potential problem only, the barrier-controlled characteristics in weak inversion and weak injection (punch-through) are produced efficiently and provide quantitative data for slopes, threshold voltages, and punchthrough voltages, as well as their two-dimensional dependence on device geometry, doping, and terminal voltages. Examples are presented for NMOS transistors with various enhancement and buried channel implants. The program is useful both as a pre-selector for structures to be simulated with a more elaborate two-dimensional potential and transport program and as a generator of parameters for a device model in a circuit simulator.

Fundamental equations describing carrier transport, current continuity, and potential distribution are used in a finite-difference scheme to model switching phenomena in semiconductor power devices. An irregular and variable mesh approach is introduced that can reduce computation time by 40%. If the device structure satisfies certain conditions, the method works even more effectively. The program is used to analyze gate-turn-off (GTO) thyristor and static-induction thyristor (SIT) switching. Carrier concentration, potential, and current distribution transients during switching of the devices are shown. The current squeeze and concentration during turn-off in the GTO are related to the gate structure. The effective channel width of the SIT is also determined through numerical analysis.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A subthreshold model for use in circuit simulation software is described. The model includes representation of nonuniform substrate impurity concentrations and short-channel and narrow-channel effects, while being simple in form. It has been developed in concert with an automated parameter-extraction methodology. The model adds only one parameter to the existing strong inversion model with which it is fully integrated. The accuracy and computational efficiency are suitable for circuit simulation. The results of an extraction carried out on nMOS transistors with channel widths from 70 to 0.9 mu m and channel lengths from 35 to 1.25 mu m over a wide range of bias conditions are described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A high-performance NOT logic gate (inverter) was constructed by combining two identical metal-insulator-semiconductor field-effect transistors (MISFETs) made on an individual CdS nanobelt (NB). The MISFETs, which used high-κ HfO2 dielectrics as the top-gate insulator layer, show excellent performance, such as low threshold voltage (∼ −0.1 V), a high on/off ratio (∼108), small subthreshold swing (∼65 mV dec−1) and threshold voltage hysteresis (∼30 mV). The supply voltage for the inverter can be as low as 1 V with a voltage gain as high as 14. When the supply voltage is 7 V, the voltage gain is 72, which is the best reported value, as far as we know, for the inverters based on NB/NW n-channel MISFETs. Besides, the inverter can work in a larger input range with highly stable output voltages. Their high output voltages can make full use of the supply voltages, and their low output voltages can be close to zero. NAND and NOR logic gates have been constructed by assembling three such CdS NB MISFETs, which show high performances as well. The operating principle of the inverter is discussed in detail.

This paper explains our investigation of the effect on 32 nm PMOS device threshold voltage (VTH) by four process parameters, namely HALO implantation, Source/Drain (S/D) implantation dose, compensation implantations, and silicide annealing time. Taguchi method determines the setting of process parameters in experimental design while analysis of variance (ANOVA) determines the influence of the main process parameters on threshold voltage. The fabrication processes of the transistor were performed by ATHENA fabrication simulator, while the electrical characterization of the device was done by an ATLAS characterization simulator. These two simulators were combined and the results were analyzed by Taguchi’s method in order to aid in design and optimizing process parameters. Threshold voltage (Vth) results were used as the evaluation parameters. The results show that the VTH value of –0.10319 V is achieved for a 32 nm PMOS transistor. In conclusion, by utilizing Taguchi’s method to analyze the effect of process parameters, we can adjust threshold voltage (VTH) for PMOS to a stable value of –0.10319 V that is wellwithin ITRS prediction for a 32 nm PMOS transistor. Key words: 32 nm PMOS device, HALO, compensation implantation, S/D implantation,threshold voltage, Taguchi’s method.

VLSI reduces the dimensions of MOS transistors so far that the product of channel length L and hot-electron critical field E C becomes comparable to or smaller than the transistor operating voltages. These transistors are classified as hot-electron MOS (HEMOS) transistors. On the basis of a hyperbolic velocity-field characteristic, a powerful nonlinear analytical model both for conductive and capacitive contributions is presented, which covers the triode and saturation regions continuously. The crucial parameter is the pinch-off field E G , for which a sensitive measurement technique is described. Static and dynamic simulations are in good agreement with 2-µm transistors and circuits, self-aligned by ion implantation. Expressions are developed for transistor transconductance, output resistance, available voltage gain, and effective input capacitance as well as inverter supply voltage, threshold voltages, ratio, noise margin, power dissipation, and delay time. These quantities are in terms of the characteristic product of channel length L and pinch-off field E G so that the effects of scaling into the submicron regime can be predicted as demonstrated by the design parameter set for a 5-fJ inverter with a 0.5-µm HEMOS driver transistor.

A new foveated CMOS image sensor has been designed and fabricated. The photocell elements transform the light into current, and then, in a continuous way, into voltage without charge integration. This kind of sensing cell has been already employed in image sensors for normal cameras, but never in foveated sensors. The presented sensor tries to emulate the human eye pixel resulting in a sensor with a space variant distribution of pixels. Consequences of this distribution are the different size of the sensing elements in the pixel matrix, the non orthogonal shapes of the different elements that integrate the pixel, and, as a result, the different response of every cell in the sensor. A scaling mechanism is needed due to the different pixel size from circumference to circumference. A mechanism for current scaling is presented. This mechanism has been studied along with other effects, as the narrow channel effect on submicron MOS transistors, and the influence of the logarithmic response of these special kinds of sensing cells. The chip has been fabricated using standard 0.7 /spl mu/m CMOS technology.

In this paper, we present novel simulation results including threshold voltage (VTH) dispersions caused by process variations for highly scaled NOR-flash memories. Fully 3-D process and device simulations are applied to calculate both of a cell (or drain) current and an F-N current with a realistic device shape. Owing to the narrow channel effects, not only the cell current but also the F-N current is found to be sensitive to the shapes of an active area and a floating gate. The dependence of the currents on the device shape is strongly related to the degradation of the VTH dispersion and hence makes it difficult to miniaturize the memory cell. In addition, we propose a suitable cell structure in order to control the VTH dispersion.

A technique to utilize GaAs insulated gate field effect transistors (IGFEI's) with large surface state densities in digital integrated circuits is described. In this technique, the threshold voltage is electrically set to obtain enhancement-mode characteristics of the IGFET's. Due to change in surface charge with time, these circuits will not function at very low frequencies. Several advantages of this IGFET technology over other enhancement-mode GaAs technologies are presented.

A high-throughput on-chip monitoring circuit with a digital output is proposed for the variations of the NMOS and PMOS threshold voltages. A voltage-controlled delay line (VCDL) and a time-to-digital converter (TDC) are used to convert a small difference in analog voltage into a large difference in time delay. This circuit was applied to the transistors of W = 10µm and L = 0.18µm in a 16 × 16 array matrix fabricated with a 0.18-µm process. The measurement of the threshold voltage shows that the maximum peak-to-peak intra-chip variation of NMOS and PMOS transistors are about 31.7mV and 32.2mV, respectively, for the temperature range from −25°C to 75°C. The voltage resolutions of NMOS and PMOS transistors are measured to be 1.10mV/bit and 3.53mV/bit at 25°C, respectively. The 8-bit digital code is generated for the threshold voltage of a transistor in every 125ns, which corresponds to the 8-MHz throughput.

A two-dimensional model of a metal-semiconductor-metal (MSM) ZnO-based photodetector (PD) is developed. The PD is based on a drift diffusion model of a semiconductor that allows the calculation of potential distribution inside the structure, the transversal and longitudinal distributions of the electric field, and the distribution of carrier concentration. The ohmicity of the contact has been confirmed. The dark current of MSM PD based ZnO for different structural dimensions are likewise calculated. The calculations are comparable with the experimental results. Therefore, the influence with respect to parameters s (finger spacing) and w (finger width) is studied, which results in the optimization of these parameters. The best optimization found to concur with the experimental results is s = 16 \mu m, w = 16 \mu m, l = 250 \mu m, L = 350 \mu m, where l is the finger length and L is the length of the structure. This optimization provides a simulated dark current equal to 24.5 nA at the polarization of 3 V.

Improved planar isolation with buried-channel MOS FET's