Automated parameter extraction and modeling of the MOSFET below threshold

In this paper, a split-flow channel layout with one (group) inlet and two (group) outlets is adopted, based on computational fluid dynamics technology, and compared with the current commonly used channel with one (group) inlet and one (group) outlet emitter. On the premise of the same outlet spacing, the pressure–flow relationship curve and slope of the split-flow emitter were analyzed under the three channel layouts of non-return, single-sided re-entry, and bilateral re-entry, with different channel widths and lengths. When exploring the influence of the channel layout and size on the hydraulic performance of split-flow emitters, the results showed that when the split-flow emitter with a non-return channel is adopted and the hydraulic performance is not reduced, the single-side channel length is half that of the one-in-one-out emitter, meaning the channel width needs to be reduced by 15%. When the channel layout is a single-sided channel re-entry, the hydraulic performance is better than that of the one-in-one-out emitter; if the hydraulic performance of the two remains unchanged, the channel width can be increased by 10% or the single-sided channel length can be reduced by 20%. When the channel layout is a bilateral channel re-entry, the channel width can be increased by nearly 30% if the hydraulic performance of the 2 is consistent, and the single-side channel length is increased by about 50%. When the split-flow emitter adopts a non-return channel layout, the channel width needs to be reduced to ensure the hydraulic performance is consistent. If the layout of single-sided channel re-entry or bilateral channel re-entry is adopted, the hydraulic performance is better than that of the one-in-one-out emitter and the hydraulic performance of the two is consistent. Thus, the channel length can be reduced or the channel width increased, which is beneficial for improving the anti-clogging performance of the emitter.

A simple behavioral SPICE model for the SiC DIMOSFET is proposed based on the understanding of the power MOSFET device terminal behavior (Figure 1). SiC Power MOSFETs show a tremendous potential for high temperature electronics applications [1-3]. However, there are very few SPICE models are available for Computer aided simulations [4-5]. The aim of the model development is to reuse the available built-in FET models of the regular lateral MOS devices of the commercial SPICE simulator. The advantage of the model is the limited number of required parameters, which can readily be extracted from simple terminal measurements or from standard datasheets, using the algorithmic and empirical approach as followed in this model development. The SPICE parameters of the model are extracted from the test data. A Power DIMOSFET test device, fabricated in 4H-SiC, is tested with the collaboration of Cree Research Inc., Raleigh, North Carolina. The model especially considers silicon carbide material and process related parameters that affect the device performance. The model can be described as a sub-circuit within the same SPICE code and can be run in any commercial SPICE simulator. Since DIMOS is a power device, its channel length, width, and other device dimensions are big enough to neglect the second order effects in the model equations, and the simulation can be carried out as SPICE level 1 or level 2. The model can be used to simulate either p-channel or nchannel SiC power MOSFET devices over a wide range of currents and voltages. A custom DC measurement system is used to facilitate the DC characterization of the SiC-DIMOSFET test device (Figure 2). DC characterization includes the measurement of device output characteristics (ID vs VDS), transfer characteristics (ID vs VGS), small signal parameters such as transconductance (gm), output conductance (gd), output resistance (ro), mobility (µ), etc. A Hewlett Packard HP4145B Parameter Analyzer is used for two primary measurement tasks: measurement of the output characteristics and the transfer characteristics of the test device. A similar measurement system is also used to measure the capacitances such as gate-source capacitance (CGS), gate-drain capacitance (CGD), and drain-source capacitance (CDS). A Keithley 590 C-V analyzer is used to measure the capacitances. The parameters of the sub-circuit model are extracted from the device terminal characteristic measurements. The value of threshold voltage, VTO and process trans-conductance parameter, KP are obtained from Figure 3 and 4. Reverse voltage blocking diode saturation current, IS and source resistance, RS are calculated from block mode operation. Rdrift is obtained from high output current measurement. Oxide thickness, TOX, channel width, W, channel length, L, breakdown voltage, Vbreak are taken from datasheet of the test device. A chopper circuit is built on a test board to measure the switching characteristics of the test device. An input pulse train of square-wave (0-5V peak-peak) for the frequency range of (1 kHz-50 kHz) is applied to the input, and the corresponding output is observed. The switching behavior is also simulated using the developed sub-circuit model. The measured wave-shapes and the simulated wave-shapes at 10 kHz are shown in Figure 5 and 6, respectively. The simulation results matched very well with the measurement. It is observed from the switching characteristics that the device can be operated for the frequency range of (0-20 kHz). The developed SPICE model can be used reliably in circuit simulation for the low voltage low power applications.

A dye-sensitized solar cell model implementable in electrical circuit simulators

A numerical two dimmensional simulation has been used to demonstrate the effect of IGFET channel width on threshold voltage. The computed results agree well with experiments and are used to build an understanding of the mechanism. Potential, field and carrier concentration distributions are used to provide a picture of the geometric interactions.

A model of mini heat sink with microchannels was developed to obtain homogeneous heat transfer capability. The channels are constructed in the form of eight triangular arrays based on a square substrate. Air is sucked from the periphery to the center of the substrate by a vacuum pump and heat transferred from the bottom surface of substrate can be removed by air flowing through channels. Corresponding to the given heat transfer power and the target temperature of substrate, the relationship among length, width and depth of channel was analytically established. By numerical simulation, local pressure drops at the joint of channels and air duct are first obtained and then the dimensions of each channel in a triangular array can be determined one by one. The investigation reveals that the widths of channels will vary with their depths, lengths and pressure differences between two ends. Since all channels are required for the same cooling power, the homogeneous heat transfer of heat sink can be realized. By assembling a certain number of heat sink units, the area of dissipation of heat sink can be enlarged and contoured to fit close to heating surface.

Performance metrics of current transport in pristine graphene nanoribbon field-effect transistors using recursive non-equilibrium Green's function approach

The authors describe a new narrow channel effect by quantum mechanical effects in ultra-narrow MOSFET's. Threshold voltage increase is observed at room temperature in ultra-narrow MOSFET's whose channel width is less than 10 nm. This result is in excellent agreement with simulation that takes account of quantum confinement in the silicon narrow channel, indicating that the increase in threshold voltage is caused by the quantum mechanical narrow channel effect.

The aim of this paper is to create an education tool to estimate the losses and the dynamic behavior of the junction temperature of a semiconductor device, to be employed in a simulation software of electrical circuits. It must be highlighted that the temperature is one of the most important variables to be controlled in a switch-mode power converter and presents a great impact on converter efficiency and power density. Due to the lack of a simple tool to analyze the thermal behavior of a static converter, this paper proposes an algorithm to predict the losses (conduction and switching) and the temperature behavior in a semiconductor device. Using this algorithm the heat-sink design can be optimized in order to project a converter with high power density. The methodology which easily extracts the loss and thermal models, without huge computational efforts, is demonstrated. The proposed approach can be used as an educational tool, since it can be easily implemented in a circuit simulation software, assisting students of Power Electronics. It is important to note, that experimental results are presented to validate the proposed approach.

A prototypical, general socio-economic system of human migration is formulated and solved as an electronic circuit. In such systems that possess multiple classes, the equilibrium conditions are equivalent to a variational inequality, rather than to an optimization problem. The circuit was solved using circuit simulation software. The equilibrium utilities and populations of the different classes of migrants at the locations are then recovered directly from the circuit simulation results. The dynamical adjustment processes of the system are obtained from the transient solution. >

The use of a positive photoresist (PR) as a phosphorus-ion implant mask for defining the source and drain of a MOS FET suffers from outgassing and deformation of the resist when high energy ions (150 keV) and a high dose (5×1015 P+/cm2) are involved. This deformation affects the dose uniformity and MOS FET channel length. Here we compare PR masks with those made up of a baked mixture of photoresist and a thermal free radical (PR+TFR) as suggested by Kluge and Elie.1 During the preimplant bake the thermoplastic deformation of the PR+TFR mask is significantly lower than that of the PR mask, but there is no significant difference between the deformation of the two masks during implantation providing the preimplantation bakes are the same. We have made MOS FET’s with channel length as defined by the mask (Lmask) varying from 0.15 to 1.600 mil(3.8 to 4 μm) and have visually measured Lmask following the preimplantation bake. By measuring the MOS FET characteristics (in the linear region) we can determine the effective channel length and compare this with Lmask over a wide range of values. The deformation of the resist can be reduced by using thinner resist and be made negligible by substituting low temperature vacuum baking (prior to implantation) for the conventional high temperature air bake.

The equivalent impedance curve of a 40W electrodeless fluorescent lamp is measured. A simulation circuit is used in the circuit simulation software (orCAD). The simulated results are compared with the experiments. With the operation frequency increase, the error between the simulation and experiment is increase from 3.3% (198KHz) to 20.1% (233KHz). The analysis of the increase of error has also been discussed

The Ω-Gate nanowire (NW) SOI nMOSFETs is an excellent candidate for future technology nodes. The goal of this work is to study the Ω-Gate NW SOI nMOSFET working in subthreshold region for low-power low-voltage (LPLV) application, with special attention on a possible parasitic drain current conduction. The studied devices are Ω-Gate nanowires SOI nMOSFETs that were fabricated at CEA-LETI/France with the following characteristics: the effective oxide thickness (EOT) of 1.3nm, the buried oxide thickness (toxb) of 145nm and the channel height (Hfin) of 10nm with three channel widths (Wfin) 220, 40 and 10nm and four channel lengths (L) 40, 100, 200nm and 1µm. Figure 1 presents the curve of the drain current (IDS) as a function of gate voltage (VGS) from which the electrical parameters such as threshold voltage (VT) and subthreshold swing (SS) (Fig.2) were extracted. From figure 2 it is possible to see that short channel devices present a SS degradation as well as present a VT variation for all channel widths, improving for narrow width as expected. However, focusing on VT behavior, an abnormal reduction on the VT values is observed for wider channel width even for long devices. Aiming to better understand this unexpected behavior, some simulations were performed using TCAD Sentaurus, Synopsis®. Figure 3, shows the simulated transfer curve for device with the same characteristics of the experimental. It is observed that it was necessary to insert the interface charges of 5x1011cm-3 to have a good agreement of the simulated with the experimental data. Figure 4 shows the simulated I­DS xVGS for several different fixed interface charges on the back interface (channel/buried oxide) in order to simulate a radiation effect on the devices. The interface charges were varied from 5x1011cm-3 up to 1x1013cm-3. Based on the simulations it is possible to notice that the increase of interface charges causes a parasitic conduction from drain to source at the back interface. Aiming to analyze the back conduction, three different values of IDS were adopted, as can be seen in figure 4B. Analyzing the current density on the front and back interface in figure 5, it can be noted that on the first point, that is located on the subthreshold slope (fig.5A), the conduction is mainly composed by the back interface for all fixed charges level. When getting closer to VT (Fig.5B) the conduction by the front interface starts to increase but the device characteristics is still affect by the back conduction and then after VT (Fig.5C) the front interface predominates. The transition of predominant conduction from the back to the front interface usually causes an abnormal IDS behavior that can be seen in the inset presented in figure 4B, where a kind of kink is clearly observed in the curves which the fixed charges is higher than 3x1012cm-3. Since the EOT is very thin, and the Hfin is 11nm, for fixed charges smaller than 3x1012cm-3 the usual behavior degradation caused by back conduction (the SS increase or a hump in the subthreshold region) is not observed in the simulated results. This unexpected result can be explained by the theoretical values of SS for the two different situations: 1) front or 2) back interface conduction, presenting an insignificant variation between the front and back SS values. This behavior can also be observed from the extracted SS values from the simulations varying the fixed charges, presented in table 1. This SS immunity to back conduction happens because these devices have a very good coupling between the interfaces due to the thinner EOT. Although this device presents a higher SS immunity, the back interface conduction occurs early as the channel width becomes wider, resulting in smaller VT for all channel lengths. This behavior is more pronounced as the fixed charge increases on the back interface. This behavior can also explain the reduction on VT values for wider devices presented on the experimental results (Fig.2). The simulated fixed charges on the back interface, can represent the radiation effects on these devices, due to the thinner gate oxide, and as was showed it did not affect the SS significantly. Therefore, when thinking about operation on the subthreshold region, where the current is exponentially proportional to VGS, the devices with narrow width are the most recommended, due to the better control of the charges in the channel but since the channel is long enough to avoid the short channel effects. And as the back conduction did not affect the SS these devices are also able to operate in irradiated environments. Figure 1

This is the first paper to discuss the ON-state drain-current of a special thin-film transistor structure with a wide channel width and a narrow source/drain width in the linear region. The experimental results indicate that when the channel width is wider than the source/drain width, the side-channel current effect is generated. This effect increases the ON-state drain-current due to the additional current-flow paths existing in the side-channel regions and low channel resistance. As the side-channel width increases, the ON-state drain-current initially increases and then gradually becomes independent of the side-channel width when the side-channel width is larger than the effective side-channel width, which depends on the channel width and is largely independent of the source/drain width. This paper also demonstrates that the ON-state drain-current gain is directly proportional to the channel length and the ratio of the channel length to the source/drain width and dependent on the side-channel width.

(1) This paper selects the modern delta formed by the Ganjiang tributary in Poyang Lake. By performing high density statistical analysis of distribution channel parameters in the area using satellite images and geographic information processing software (LucaSpaceViewer 4.5.2, ArcGIS Pro 3.0.2, Global Mapper v23.1), including length, width, bifurcation angle, bifurcation frequency, and channel sinuosity, the distribution characteristics of delta distribution channels are derived and quantitatively characterized. (2) Classification and evaluation of these characteristics are carried out using factor and cluster analysis, ultimately identifying controlling factors affecting the morphology and distribution of the distribution channels. By statistically analyzing the geometric and bifurcation data of the channels, factor and cluster analysis for data reduction and classification, the channel is finally divided into three categories: Type I channels have relatively high channel length, width, sinuosity, bending amplitude, and a lower bifurcation (or confluence) growth rate; Type II channels are characterized by low channel length, moderate channel width, low sinuosity, low bending amplitude, and a high bifurcation (or confluence) growth rate; Type III channels are defined by moderate channel length, low width, high sinuosity, high bending amplitude, and low bifurcation (or confluence) frequency. (3) After excluding the influence of other factors, it was found that the main controlling factor for the morphology of the Ganjiang Delta channel is flow velocity, which is influenced by changes in the terrain slope. Flow velocity directly affects channel sinuosity, bending amplitude, and bifurcation (or confluence) frequency, and indirectly affects channel length and width.

Extensive design tools are available today to develop digital application specific integrated circuits (ASICs), but the analog and mixed analog/digital ASIC arena is lagging behind. This panel will solicit views of tool developers and ASIC designers about the needs and direction of design tools for the development of mixed analog/digital ASIC over the next five years. The availability and usability of automatic/semi-automatic software and hardware for circuit partitioning, circuit simulation, place and route, silicon compilation and testing will be appraised Educational needs of the analog/digital designer will also be included in the discussions.