Modeling and Verifying Circuits Using Generalized Relative Timing

In this paper, a scheduling algorithm for multi-processor real-time systems with relative timing constraints and resource constraints is proposed. The proposed algorithm has the capability to satisfy any timing constraints expressed as inequalities in two variables and a constant. This implies that scheduling problems imposed on various timing constraints such as end-to-end timing constraints and/or relative timing constraints, which are known to be difficult to handle, can be solved. Since the problem addressed in this paper is a generalization of some NP-complete problems, it is difficult to solve efficiently. Thus, the goal of the authors is to derive a heuristic algorithm which performs well on many instances of the problem, although in some cases it will take enormous space and time. Experimental results show that the proposed algorithm achieves a success rate of 80% in 3 minutes of computation time.

Allocation problem has always been one of the fundamental issues of building the applications in real-time computing systems. For real-time applications, the allocation problem should directly address the issues of task and communication scheduling. In this context, the allocation of tasks has to fully utilize the available processors and the scheduling of tasks has to meet the specified timing constraints. Clearly, the execution of tasks under the allocation and schedule has to satisfy the precedence, resources, and other synchronization constraints among them. Recently, the timing requirements of the real-time systems emerge that the relative timing constraints are imposed on the consecutive executions of each task and the inter-task temporal relationships are specified across task periods. In this paper we consider the allocation and scheduling problem of the periodic tasks with such timing requirements. Given a set of periodic tasks, we consider the least common multiple (LCM) of the task periods. Each task is extended to several instances within the LCM. The scheduling window for each task instance is derived to satisfy the timing constraints. We develop a simulated annealing algorithm as the overall control algorithm. An example problem of the sanitized version of the Boeing 777 Aircraft Information Management System is solved by the algorithm. Experimental results show that the algorithm solves the problem in a reasonable time complexity.

Bounded model checking for interval probabilistic timed graph transformation systems against properties of probabilistic metric temporal graph logic

Traditional scheduling models assume that the execution time of a job in a periodic job-set is constant in every instance of its execution. This assumption does not hold in real-time systems wherein job execution time is known to vary. A second feature of traditional models is their lack of expressiveness, in that constraints more complex than precedence constraints (for instance, relative timing constraints) cannot be modeled. Thirdly, the schedulability of a real-time system depends upon the degree of clairvoyance afforded to the dispatcher. In this paper, we shall discuss Totally Clairvoyant Scheduling, as modeled within the E-T-C scheduling framework [Sub05]. We show that this instantiation of the scheduling framework captures the central issues in a real-time flow-shop scheduling problem and devise a polynomial time sequential algorithm for the same. The design of the polynomial time algorithm involves the development of a new technique, which we term Mutable Dynamic Programming. We expect that this technique will find applications in other areas of system design, such as Validation and Software Verification.

A self-timed microarchitecture called KeyRing is presented, and a method for implementing KeyRing circuits compatible with a timing-driven electronic design automation (EDA) flow is discussed. The KeyRing microarchitecture is derived from the AnARM, a low-power self-timed ARM processor based on ad hoc design principles. First, the unorthodox design style and circuit structures are revisited. A theoretical model that can support the design of generic circuits and the elaboration of EDA methods is then presented. Also addressed are the compatibility issues between KeyRing circuits and timing-driven EDA flows. The proposed method leverages relative timing constraints to translate the timing relations in a KeyRing circuit into a set of timing constraints that enable timing-driven synthesis and static timing analysis. Finally, two 32-bit RISC-V processors are presented; called KeyV and based on KeyRing microarchitectures, they are synthesized in a 65 nm technology using the proposed EDA flow. Postsynthesis results demonstrate the effectiveness of the design methodology and allow comparisons with a synchronous alternative called SynV. Performance and power consumption evaluations show that KeyV has a power efficiency that lies between SynV with clock-gating and SynV without clock-gating.

Wargames, especially on historical conflicts, do not currently play much part in the booming academic use of simulation and gaming techniques. This is despite the fact that they offer rich vehicles for active learning and interactive exploration of conflict dynamics. Constraints of time, expertise and resources do make it challenging to employ wargames in academia, but a greater problem is the stigma which wargaming attracts due to its association with childish enthusiasts and its perceived deficiencies as a modelling technique. This article builds on my many years of teaching and research experience with wargames to show how playing and designing them can benefit students and scholars alike.

This paper is interested in the run-time adaptation of reconfigurable Multiprocessor System on Chip MPSoC architectures to their environment. A reconfiguration consists in the addition, removal or update of OS tasks to be executed in the different processors under real-time constraints. These tasks are with precedence constraints and exchange messages on the Network on Chip NoC that links different processors. Nevertheless, the intensive application of reconfigurations increases the frequency of the exchanged messages which become more and more important. The saturation problem of routers is then possible. We aim to prove by this research that all reconfigurable messages reach their target destinations and also respect their time constraints. Thus, the need to explore several paths instead of a faulty one is recommended. We propose a routing algorithm that allows a feasible real-time NoC after any reconfiguration scenario. This algorithm is split into two steps where the former deals with the look for minimal possible paths and the latter deals with a selected path that the messages will follow. This contribution is applied to a case study that we model by the formalism Reconfigurable Timed Net Condition Event System R-TNCES to verify temporal logic properties with the model Checker SESA.

Cyber-physical systems often encompass complex concurrent behavior with timing constraints and probabilistic failures on demand. The analysis whether such systems with probabilistic timed behavior adhere to a given specification is essential. When the states of the system can be represented by graphs, the rule-based formalism of Probabilistic Timed Graph Transformation System (PTGTSs) can be used to suitably capture structure dynamics as well as probabilistic and timed behavior of the system. The model checking support for PTGTSs w.r.t. properties specified using Probabilistic Timed Computation Tree Logic (PTCTL) has been already presented. Moreover, for timed graph-based runtime monitoring, Metric Temporal Graph Logic (MTGL) has been developed for stating metric temporal properties on identified subgraphs and their structural changes over time.In this paper, we (a) extend MTGL to the Probabilistic Metric Temporal Graph Logic (PMTGL) by allowing for the specification of probabilistic properties, (b) adapt our MTGL satisfaction checking approach to PTGTSs, and (c) combine the approaches for PTCTL model checking and MTGL satisfaction checking to obtain a Bounded Model Checking (BMC) approach for PMTGL. In our evaluation, we apply an implementation of our BMC approach in AutoGraph to a running example.Keywordscyber-physical systemsprobabilistic timed systemsqualitative analysisquantitative analysisbounded model checking

Coupling fluid–structure interaction with phase-field fracture

Endoplasmic reticulum (ER) is a communication hub for several signaling and secretory pathways that regulate the cell cycle progression. Recent studies revealed that deregulation of ER stress-induced signaling pathways are involved in the patho-genesis of cancer and Alzheimers disease. Computational analysis and verification of these pathways will provide insights into the mechanism linking ER stress with different diseases. Based on the experimental observation and our recent bioinformatics studies, we construct a quantitative model to systematically study the ER stress-induced apoptosis and survival signaling pathways. To overcome the limitations of traditional simulation techniques, a formal verification method, called Probabilistic Model Checking, was introduced and applied to formally analyze the temporal logic properties of the stochastic model, which is written in the PRISM language. Compared with the symbolic model verification method, this PRISM verification technique can not only qualitatively verify the signaling pathway model using sequential probability ratio test (SPRT), but also provide a quantitative estimation of the temporal properties using confidence interval estimation method. The probabilistic verification studies show that, overexpressed ER transmembrane proteins will promote the expression of Cyclin D, Amyloid-β and MDM2, leading to the pathogenesis of cancer and other diseases in the long term, and inhibit the apoptosis. Our work also verified that, varying IKK's expression level will influence the number of NFκB molecules in the nucleus, which explained why IKK inhibitor could inhibit tumorigenesis. The proposed signaling pathway model and PRISM method can help our understanding of the mechanisms that link ER stress with cancer and other diseases.

In this paper, a scheduling algorithm for multi-processor real-time systems with relative timing constraints and resource constraints is proposed. The proposed algorithm has the capability to satisfy any timing constraints expressed as inequalities in two variables and a constant. This implies that scheduling problems imposed on various timing constraints such as end-to-end timing constraints and/or relative timing constraints, which are known to be difficult to handle, can be solved. Since the problem addressed in this paper is a generalization of some NP-complete problems, it is difficult to solve efficiently. Thus, the goal of the authors is to derive a heuristic algorithm which performs well on many instances of the problem, although in some cases it will take enormous space and time. Experimental results show that the proposed algorithm achieves a success rate of 80% in 3 minutes of computation time. © 1997 Scripta Technica, Inc. Syst Comp Jpn, 28(3): 52–61, 1997

This paper discusses a class of mission planning problems in which mission objectives and relative timing constraints are specified using the linear temporal logic language LTL-x. Among all mission plans that satisfy the LTL-x specifications, it is desired to find those minimizing a given cost functional. We show that such an optimization problem can be formulated as a mixed-integer linear program, and present an algorithm for this purpose. This algorithm mainly relies on a novel systematic procedure which converts a given LTL-x formula into a set of mixed-integer linear constraints. The approach presented here can be used for multiple-UAV mission planning purposes, allowing the operator to specify complex mission objectives in LTL-x in a very natural manner; the proposed algorithm constructs the optimal mission plan satisfying the given LTL-x specification. Examples for practical problem sizes are presented and discussed in the paper.

We present a tool that performs real time analysis and priority assignment for software tasks in a mixed hardware software system with a custom run time scheduler. The tasks in hardware and software have precedence constraints, resource constraints, relative timing constraints, and a rate constraint. A dynamic programming formulation assigns the static priorities such that a hard real time rate constraint can be predictably met. We describe the task control/data flow extraction, runtime scheduler implementation, real time analysis and priority scheduler template. We show how our approach fits into an overall tool flow and target architecture. Finally, we conclude with a sample application of the system to a design example.

Conformance testing amounts to verifying adequacy between the behaviors and the specified behaviors of an implementation. In this paper, we handle model-based conformance testing for data-flow critical systems with time constraints. Specifications are described with a formal model adapted for such systems and called Variable Driven Timed Automata (VDTA). VDTA are inspired by timed automata but they use input/output communication variables, allowing clear and short specifications. We present a conformance relation for this model and we propose a symbolic test selection algorithm based on a test purpose. The selection algorithm computes the variations on inputs allowing to reach an expected state of the implementation. Then we propose an on-line testing algorithm.

The conventional synchronous design approach is not suitable for implementing self-timed circuits on FPGAs. When design tools try to meet synchronous circuits timing constraints, they can violate self-timed setup timing constraints. This paper proposes a new methodology for implementing self-timed circuits in modern FPGAs using the Xilinx Hierarchical Design flow and a convenient architecture of a configurable delay element. Reported simulation results, in accordance with static timing analysis, show that the self-timed timing constraints are satisfied using our design methodology.