Introducing KeyRing self‐timed microarchitecture and timing‐driven design flow

Interposer-based 2.5-D integrated circuits (ICs) enable the chip-level reuse of hard intellectual properties (IPs), also known as chiplets. Such system-level integration shortens the design cycle considerably for large-scale and heterogeneous chips. Besides traditional interposers, which only provide passive elements and routing, active interposers are furthermore comprised of logic components. When implemented carefully using a dedicated electronic design automation (EDA) flow, an active interposer can significantly improve the design quality and flexibility for 2.5-D ICs. In this article, we present a complete EDA flow and design strategies targeting, such active interposer-based 2.5-D ICs. Our key contributions include the coanalysis of power, performance, signal and power integrity, and the related co-optimization of chiplets and the active interposer. Our benchmark is a 64-core RISC-V architecture, organized into multiple chiplets and interconnected by a system-level network-on-chip (NoC). For efficiency, we embed the NoC routers and integrated voltage regulators (IVRs) into the active interposer. Moreover, we integrate security monitors into the interposer-based NoC to protect the system and its shared memories against adversarial traffic. The simple yet powerful benefit of this implementation is to offer security by construction, as it is based on a clear physical separation between critical and trusted components (the system-level NoC) versus commodity components (the chiplets). We contrast our active, secured design to a passive, unsecured design baseline of the same RISC-V benchmark and find that the active design reduces the silicon area by 18.5%, power by 3.2%, and IR drop by 73.7%.

The design of digital systems has its mainstay in the electronic design automation flows which act as crucial instruments to reduce the effort to realize complex computing platforms. In this work, we investigate the possibility of integrating side channel security analyses within the existing FPGA design flow, to provide a feedback to the hardware designer in a prompt and effective way. To this end, we realize an analysis framework which detects side channel leakage on the power consumption side channel at two well established checkpoints in hardware design, i.e., post synthesis and post implementation. We report the results of the proposed framework when integrated within the commercial Xilinx Vivado design toolchain. As a case study, we employ an open source SoC running a software version of the AES block cipher and provide a taxonomy of the side channel information leakage. The reported results highlight how our approach is able to provide precise insights on the sources of information leakage in the hardware design at hand. In particular, we show that the results of the simulations at post synthesis and post implementation stages provide complementary sets of insights on the information leakage, which, thanks to our methodology, can be traced back to architectural components which are the culprits of the said leakage.KeywordsDesign automation and toolsFPGA design flowSide channel analysis

Driven by Moore’s law, the chip design complexity is steadily increasing. Electronic Design Automation (EDA) has been able to cope with the challenging very large-scale integration process, assuring scalability, reliability, and proper time-to-market. However, EDA approaches are time and resource-demanding, and they often do not guarantee optimal solutions. To alleviate these, Machine Learning (ML) has been incorporated into many stages of the design flow, such as in placement and routing. Many solutions employ Euclidean data and ML techniques without considering that many EDA objects are represented naturally as graphs. The trending Graph Neural Networks are an opportunity to solve EDA problems directly using graph structures for circuits, intermediate RTLs, and netlists. In this paper, we present a comprehensive review of the existing works linking the EDA flow for chip design and Graph Neural Networks.

In modern IC design, circuit designers often need to manually operate and move data among different EDA (Electronic Design Automation) tools. If these tools were installed in separate computers, due to the license and system requirements, the design flow will be frequently interrupted, to handle the dreary data movement work, and the design efficiency will thus be reduced. To alleviate the above problem, a seamless and efficient design flow would be a must. The aim of this paper is to propose a service-oriented integrated EDA environment that can improve the smoothness of the design flow and consequently increase the overall design productivity. In our approach, a multi-agent framework based on JADE platform is used to manage distributed EDA tools, which are encapsulated as agent services. Mobile agents are allowed to autonomously and concurrently migrate among computers to access services for IC designers. To facilitate that, a scripting language is designed for mobile agents to allocate tasks, cooperate with each other, and select appropriate services. To demonstrate the feasibility of our method, an Integrated Circuit Design Cycle Assistant System (ICDCAS) for simplifying the manual operations in IC design cycles is developed by combining two EDA tools: ModelSim and Xilinx ISE. The implemented system proves to have the features of time saving and being free of mistakes incurred by manually operating and configuring the sophisticated EDA tools.

We propose an algorithm for monitoring timing constraints to satisfy confidence threshold requirements when there is uncertainty in the exact timing of event occurrences. In our model, a timed event trace is examined for possible satisfaction/violation with respect to a given set of timing constraints. Every event occurrence has a timestamp given by a time interval. Assuming that the time of occurrence is uniformly distributed over the time interval, our algorithm determines whether the probability that a timing constraint has been satisfied exceeds a specified threshold value. Timing constraints are composed of deadline and delay constraints for which satisfaction probabilities are defined. A confidence threshold is a minimum satisfaction probability of the timing constraint. A timing constraint is violated if the confidence threshold is not reached by the timed event trace. We present a ptime monitoring algorithm for detecting timing violation by finding the earliest expiration time (EET) of the deadline timer for each of the cases P = 100%, 50% /spl les/ P < 100%, and 0% < P < 50%, where P is the confidence threshold of the timing constraint. We give a derivation of the implicit constraints needed for computing the EET, and we show how to use an all-pairs shortest path algorithm to compute the implicit constraints.

The application of machine learning (ML) in Electronic Design Automation (EDA) has emerged as a powerful approach to address the growing complexity and scale of modern VLSI systems. This chapter explores how ML techniques are integrated into various stages of the EDA flow to improve efficiency, accuracy, and design productivity. Supervised, unsupervised, and reinforcement learning methods are discussed in the context of logic synthesis, placement and routing, timing and power optimization, and design rule checking. By learning from historical design data, ML models enable faster design space exploration, early prediction of design bottlenecks, and adaptive optimization under complex constraints. The chapter also highlights the role of ML in yield prediction, reliability analysis, and test optimization for advanced technology nodes. Challenges such as data availability, model generalization, and interpretability are addressed, emphasizing the need for close integration between ML models and traditional EDA tools. Overall, this chapter underscores the transformative impact of machine learning on next-generation EDA methodologies.

Electronic Design Automation (EDA) technology represents the development direction of modern electronic design technology. This paper presents the traditional digital circuit design method, carefully introduces a top-down hierarchy design method, analyzes advantages and disadvantages of traditional experimental teaching, and proposes the application of EDA experimentation in digital circuit design. It is comprised of hardware and software. Numerical Control Frequency divider is taken as a typical example to display EDA experimental applications. An EDA experimental system based on FPGA/CPLD can achieve automated design of digital circuit quickly and easily, and thus it provides a good platform for the logic design and development of medium and large-scale digital circuit.

The use of digital print provides unique opportunities to automate the printing process, revamp production steps, better utilize resources, and enhance productivity. This paper highlights the key role that electronic design automation (EDA) can play in the maturation of the digital print automation field. It first describes basic concepts in digital printing and digital commercial print services. Next it describes the application of discrete-event simulation to policy management and performance evaluation, and dynamic resource management using EDA flows based on scheduling and resource binding.

Boolean Satisfiability (SAT) is a widely used modeling tool in Electronic Design Automation (EDA). It finds application in test pattern generation, delay-fault testing, equivalence checking and circuit delay computation, among many other problems. This paper starts by describing how Boolean Satisfiability algorithms can take circuit structure into account when solving instances derived from combinational circuits. Afterwards, it shows how recursive learning techniques can be incorporated into Boolean Satisfiability algorithms. The proposed algorithmic framework has several natural applications in EDA. Moreover, potential advantages include smaller run times, the utilization of circuit-specific search pruning techniques, avoiding the overspecification problem that characterizes Boolean Satisfiability testers, and reducing the time for iteratively generating instances of SAT from circuits. The experimental results obtained, on a large number of benchmark examples in different problem domains, illustrate the effectiveness of the proposed techniques.

An approach to timing analysis of cyclic concurrent programs is presented. GR/sub 0/ path-expressions are used to describe synchronization and concurrency of atomic operations in cyclic concurrent programs. The behavior of a cyclic concurrent program is represented as a partial order of atomic operations, and a technique to derive this partial order from a GR/sub 0/ program is developed. Given the execution times of the individual atomic operations of a GR/sub 0/ program and a set of timing constraints, our timing analysis technique uses the partial order to determine whether the concurrent program, when executed, will satisfy the set of timing constraints. The timing analysis technique can be completely automated.

Electronic Design Automation (EDA) tools are central to Very Large Scale Integration (VLSI) design, where numerous parameters govern the Quality-of-Result (QoR) metrics, including performance, power, and area. The high dimensionality of the parameter space, coupled with complex interactions, makes manual tuning inefficient and hinders the scalability of automated methods. Existing methods typically treat parameters as flat vectors, neglecting the EDA flow’s hierarchical causal structure, where early-stage decisions constrain later downstream stages. To address this, we propose CausalTuner, a causality-aware design space exploration framework for efficient parameter tuning. It employs a hybrid causal attention mechanism to capture stage-wise parameter interactions and embeds them into deep kernel Gaussian processes for accurate and generalizable surrogate modeling. The causal exploration strategies enhance sampling efficiency. Experiments show that CausalTuner outperforms state-of-the-art methods in both final QoR and efficiency.

Aging is an important determinant for the reliability of circuit designs and has been addressed by a number of protection techniques based on static timing analysis (STA). The timing reported by STA, however, is often too optimistic without considering the functional behavior of the circuit. Furthermore, signal probability has also been found to be a significant factor in the aging effect. As such, we present in this paper a timing-critical path analysis that takes function and aging into account as well as signal probability. Functional timing analysis (FTA) eliminates the false paths and generates more accurate timing. Furthermore, machine learning can be used to build models for predicting the timing of each cell for various aging lifetimes and signal probabilities. Experimental results indicate that there can be a difference of up to 6% on path delay between STA and FTA. The path ranks also differ for most of the benchmark circuits after considering aging with signal probability, resulting in the delay differences of up to 6.12 %. In conclusion, it is necessary to consider function, aging, and signal probability simultaneously when analyzing timing-critical paths in a circuit design.

This is a case study of the use of graph similarity to correlate the timing models obtained from two electronic design automation (EDA) static timing analysis tools (Altera's Quartus II software versus Synopsys PrimeTime). Timing models are data modelled from the post-layout netlist and parasitics extraction. The field programmable gate array's (FPGA) timing model is used by customers to optimize their designs. As mask designs are constantly revisioned, new timing models are generated and thus the Quartus II software must constantly be updated with the new models. A verification needs to be carried out at every new iteration of timing models to ensure the regression testing of timing models is stable and reliable. This case study discusses one such verification methodology. A timing graph consists of nodes and edges. Edges have weights attached to them that can denote some characteristic, such as timing arc delays in this case. Out of the many graph similarity algorithms in the field, the most cited are edit distance similarity, neighbourhood matching, spectral matching and belief propagation. Neighbourhood matching, which was used in this study, is a point-to-point matching of a node's similarity score based on its neighbourhood's similarity score. The timing graph from the Quartus II software was generated with an in-house Tcl scripting language applications programming interface. The timing graph from PrimeTime was generated from its timing reports. An algorithm was postulated to calculate graph similarity based on edge weights of the graphs. The algorithm compared both graphs and produced a matrix of graph similarity scores for all paired nodes. The algorithm was tested on five data paths taken from the two EDA tools under evaluation. Our results showed good correlation between intuitive similarity measure and our algorithmic calculation.

Convolutional Neural Networks (CNNs) are widely used in computer vision, natural language processing, and so on, which generally require low power and high efficiency in real applications. Thus, energy efficiency has become a critical indicator of CNN accelerators. Considering that asynchronous circuits have the advantages of low power consumption, high speed, and no clock distribution problems, we design and implement an energy-efficient asynchronous CNN accelerator with a 65 nm Complementary Metal Oxide Semiconductor (CMOS) process. Given the absence of a commercial design tool flow for asynchronous circuits, we develop a novel design flow to implement Click-based asynchronous bundled data circuits efficiently to mask layout with conventional Electronic Design Automation (EDA) tools. We also introduce an adaptive delay matching method and perform accurate static timing analysis for the circuits to ensure correct timing. The accelerator for handwriting recognition network (LeNet-5 model) is implemented. Silicon test results show that the asynchronous accelerator has 30% less power in computing array than the synchronous one and that the energy efficiency of the asynchronous accelerator achieves 1.538 TOPS/W, which is 12% higher than that of the synchronous chip.

As the technology node scales down below nanometer, the design rules significantly increase, which in turn results in the huge search problems of the chip design with an early-stage technology. DTCO (Design-Technology Co-Optimization) becomes a key methodology in semiconductor industry to overcome the limitation of physical scaling and transistor density, and to improve performance and power efficiency [1-2]. However, DTCO induces huge increase of design spaces in physical implementation since chip designers should tune the technology related variables along with the conventional design variables at the early technology stage. ML (machine learning) is a powerful technique when tuning and optimizing such complicated parameters in technology and design [3]. Synopsys DSO.ai (Design Space Optimization AI) is an early innovator of ML (Machine Learning) in EDA (Electronic Design Automation) area, where the tool uses advancements of RL (Reinforcement Learning) to effectively search the massive design space for global near-optimal targets [4]. In this paper, we report DSO.ai applications on 3nm technology and designs, such as PPA (Performance-Power-Area) improvements in both HP (high performance) and HD (high density) libraries, NDR (non-default rule) routing on both clock and signal nets, LP (layer promotion), density control, routing wire and via cost tuning, and more. Furthermore, we utilize ML capability in searching and optimizing technology parameters, e.g., key design pitches and design rules, as well as design parameters, e.g., via/wire cost, placeholder densities, legalization and routing strategies, and other EDA settings, to maximize PPA metric and to minimize DRC violation. Our goal is to find the best values of the initial parameters from an early technology and design stages and to encapsulate them in RM (Reference Methodology) script to provide the designer with the mega switch in entire design flows. Parameter range (to be explored) and evaluation metrics (to score QOR) are defined, then DSO.ai explores search spaces and trains itself to minimize the optimization cost. Optimized parameter values are evaluated against the reference parameters to reproduce the benefit across various designs and technology collaterals. In this manner, different parameters can be optimized given design methodology. This iterative process can be extended to optimize all design technology parameters to maximize PPA on 3nm design technology and designs and beyond. Proposed approach applied to optimize achievable core area and improve max frequency, respectively. Design flow with ML-assisted parameter could reproduce improvement across the different size and different styles of the benchmark designs. Optimization for achievable core area could reduce -0.5% at cell-driven design and -0.6% at route-driven design. Optimization for performance could improve the frequency of +1.42% at cell-driven design and +1.43% at route-driven design in Samsung 3nm technology.