Modelling the single-electron transistor with piecewise linear functions

Scaling of semiconductor devices has pushed CMOS devices close to fundamental limits. The remarkable success story of Moore's law during the last 40 years, predicting the evolution of electronic device performances related to miniaturization, has always been respected. However, electron device challenges are now much more complex. In order to keep Moore's law living, device scaling-down is not enough. So called material and geometry technology boosters have been introduced. High-k dielectrics, silicon-on-insulator substrates or strained silicon are some booster examples, used at sub-micron scale. This work proposes an investigation of a hybrid CMOS/SET technology, based on gate-all-around silicon nanowires. It is shown that a silicon nanowire can serve two device purposes: first as innovative 3D metal-oxide-semiconductor field effect transistor (MOSFET), and second as single electron transistor (SET). The SET is a solid-state electronic device, which controls the transport of a unique or a few electrons. SET functions are not limited by its nano-scaled structure. The smaller is the better. SET consists of a small conductive quantum dot, called island, connected to two reservoirs acting as drain and source by tunnel junctions. The size of the island should be as small as possible – typical values ranging from 1 to 4nm – in order to have room temperature operation. Electron transport from source to island, and from island to drain is controlled by a capacitively coupled gate. The nano-scale size of the island makes the carrier electrostatic repulsion efficient. This effect is called Coulomb Blockade. SET advantages are an ultra-reduced size and a very low power consumption, while SET challenges are variability related to dimension control and background charge effect, room temperature operation and a reduced fan-out. The first chapter of this thesis introduces ideas of up-to-date MOS and SET devices and shows how to combine MOS and SET to obtain original electronic functions. The second chapter is a discussion of the nanowire as a technology platform for the integration of SET devices and also presents TCAD simulation results. Key contributions are reported in chapter three. This is the original and complete description of the different top-down processes used for the integration of a gate-all-around MOS/SET platform. Samples integrated at the EPFL Center of Microtechnology (CMI) are presented. Different approaches have been studied and used in order to overcome lithographic limitations, and to have a fast and reliable integration at moderate cost. This includes auto-aligned techniques, focused ion beam prototyping, and top-down local-SOI and true-SOI nanowires. The local-SOI technique based on silicon nano-channel wires has given the best results and offers a lot of flexibility in term of wire cross-sections and shapes. Gate-all-around silicon nanowires, obtained by sacrificial etching and self-limited oxidation, with a circular 5nm diameter cross-section have been characterized. Chapter four is the validation by measurements of both SET and MOS devices. Excellent room temperature characteristics have been observed in MOS structures, while both ID-VG Coulomb oscillations and ID-VD Coulomb gap are observed on smaller structures at cryogenic temperature (T<20K). The process described has many advantages in comparison with bottom-up grown wires, such an excellent crystallinity of the channel and ohmic source-drain contacts. Finite elements simulations have also highlighted the influence of carrier mobility, channel length and cross-section shape in our defined nanowire structures. The last chapter of this report concludes this work and gives perspectives on the near future. The hybrid combination of silicon nanowire MOSFET and SET can definitely be an appealing approach in order to bridge the gap between emerging nanoelectronic devices and more traditional CMOS.

We present the perspective of CMOS electronics as a candidate for the readout purposes of sensing devices such as the Single Electron Transistor (SET) at very low temperature. Fully Depleted Silicon on Insulator (FD-SOI) CMOS devices are less susceptible to low temperature anomalies compared to bulk devices. The electrical characteristics of a typical SET are too small in comparison to usual current/voltage levels for MOS circuits and thus imposes new complications in circuit design. We present a digital readout scheme of the SET best suited for scalable design. The circuit is implemented with commercial 0.5µm SOI CMOS process operating at 4.2K. The simulation results show successful detection of 200pA drain current of an SET biased at 10µV with 15µs detection speed and static power dissipation less than 45µW.

We propose a complementary self-biasing method which enables the single-electron transistor (SET)/complementary metal-oxide semiconductor (CMOS) hybrid multi-valued logics (MVLs) to operate well at high temperatures, where the peak-to-valley current ratio (PVCR) of the Coulomb oscillation markedly decreases. The new architecture is implemented with a few transistors by utilizing the phase control capability of the sidewall depletion gates in dual-gate single-electron transistors (DGSETs). The suggested scheme is evaluated by a SPICE simulation with an analytical DGSET model. Furthermore, we have developed a new process technology for the SET/CMOS hybrid systems. We have confirmed that both of the fabricated devices, namely, SET and CMOS transistors, exhibit the ideal characteristics for the complementary self-biasing scheme: the SET shows clear Coulomb oscillations with a 100 mV period and the CMOS transistors show a high voltage gain.

Since the last decade Single electronics fascinated researchers worldwide owing to its Nano feature size, ultra-low power dissipation and high speed like novel device functionalities. But the fragility is that it suffers from few intrinsic limitations. Besides, it has been revealed that CMOS and Single Electronics are rather complementary and hybridizing them diminishes the shortcomings of each other. To the contrary hybrid CMOS-Single Electron Transistors combine both the merits of Single Electron Transistors and CMOS devices and thus it ensures to be a more convenient realization for nanometer-scale circuit design. But CMOS and Single Electron Transistors are unique in nature and require two different simulating environments; thus they have to be simulated separately. Hence two distinctive simulators are used to simulate hybrid CMOS Single Electron Transistor and it is typically more time consuming. In this regard the authors here demonstrate a probable approach to simulate both CMOS and SET in one simulator. For exemplifying the authors report a hybrid CMOS-Single Electron Transistor PLA ADDER gate using MATLAB simulator. The results mimic the ADDER logic adequately.

The moments produced by the aerodynamic control effectors on aircraft are typically non-linear functions of displacement with a region of linearity about zero displacement. In this paper we briefly review a novel approach that was developed at AFRL for solving the control allocation problem where the control moments are piecewise linear functions of the control displacement. The advantages of this approach are that it avoids cumbersome, high-order polynomial curve fits of the aerodynamic data and thus avoids solution of a non-linear programming problem. Stability and control derivatives are almost always stored in multi-dimensional look-up tables where it is assumed that the data is piecewise linear. The approach that is presented utilizes this piecewise linear assumption for the control effector moment data and accounts for non-linearities in the moment-effector relationships and position constraints on the effectors as well. The control allocation problem using piecewise linear functions is posed as a mixed-integer linear program (MILP) and solved using a freely available GNU-licensed mixed-integer linear programming code. We demonstrate two applications of the piecewise linear control allocation (PLCA) approach. The first application to be considered is to use the PLCA approach in the inner-loop control law of a re-usable launch vehicle on approach and landing. The second application is constraint estimation for trajectory reshaping and re-targeting. In order to successfully re-target a trajectory when an aircraft has experienced degraded performance due to a failure or damage to the vehicle, the effects of the failure or damage on the lift, drag, and trimmability of the vehicle must be known a priori over the entire flight envelope

Recent modern fabrication technology allows us for the fabrication of nanometer-scaled devices, which is possible to observe single electronic or single electron tunneling phenomena (Averin & Likharev, 1991; Likharev, 1988; Likharev, 1999; Hanna et al., 1991; Tucker, 1992). On the other hand, MOSFET (metal-oxide-semiconductor field effect transistor) devices with channel length below 20 nanometer (nm) are no more properly operated because the downscaling of MOS devices causes a large statistical fluctuation of the threshold voltage. A possible approach to overcome this problem is to use the single electron devices for future VLSI (very large scale integrated circuit) (Takahashi et al., 1995; Saitoh et al., 2001). Nanometer scale single electron devices have the following features, i.e., low power consumption and small size. These are key features to realize ultra high density circuits. Single electron circuits with new architecture are also possible because the basic operation of single electron devices is quite different from that of conventional semiconductor devices. There are two major requirements for single electron tunneling phenomena (Coulomb blockade) to occur (Averin & Lhikarev, 1991; Likharev, 1988; Likharev, 1999). Firstly, thermal energy 倦喋劇 must be much smaller than elemental charging energy 結態 に系 ⁄ . This ensures that the transport of charges is in fact governed by the Coulomb charging energy. This condition can be fulfilled either by lowering the temperature or by decreasing the capacitance which means to reduce the island size. Usually, experiments are performed at temperatures of a few mK and for structures with island sizes of a few hundred nanometers. Second requirement is related to tunnel resistance which must exceed the quantum resistance (h ね結態 ⁄ ≈ は.の kΩ). This condition ensures that the wave functions of excess electrons between the barriers are basically localized. On the other word, in the case of lower tunnel resistance, excess charges extend over the barriers so that no single electron tunneling event can be possible. There are several types of circuits where the single electron tunneling phenomena are being explored, such as single electron box (Likharev, 1999), single electron transistor (SET) (Tucker, 1992; Takahashi et al., 1995; Saitoh et al., 2001; Wolf et al., 2010; Sun et al., 2011; Lee et al., 2009), single electron pump (Ono et al., 2003), single electron turnstile (Moraru et al., 2011) and single electron circuits with several junctions (1D and 2D arrays) (Nuryadi et al., 2003; Nuryadi et al., 2005). A double junction system is most important single electron circuit because of a basic component of SET. At small applied voltage, the system remains in the Coulomb blockade state, and no current flows through the double junctions. On the other hand, at higher applied

The single‐electron transistor (SET) is considered as a promising alternative to CMOS devices and integrated circuits due to its ultra‐low‐power consumption. The authors propose an automatic methodology by utilising SET‐based multiway decision graph (MDG) for implementing SET architecture. MDG provides a powerful means of abstraction and can be used to manipulate a certain type of first‐order logic formula called directed formula (DF). An automatic tool has been developed that is capable of transferring the SET array into MDG DF to generate all paths of all possible reachable states, drawing an abstract diamond‐shaped network for the SET array, producing a reduced DF generated by the MDG tool and converting the reduced DF into a conjunctive normal form formula. Then, the authors use the satisfiability approach as a verification engine to verify the correctness of these conversions. The method is tested and verified using MCNC benchmarks. The results outperform approaches based on binary decision diagrams in terms of verification time, number of clauses and variables.

The infinite relaxations in integer programming were introduced by Gomory and Johnson to provide a general framework for the theory of cutting planes: the so-called valid functions, and in particular the minimal and extreme functions, can be seen as automatic rules for the generation of cuts. However, while many extreme functions are piecewise linear and therefore easy to describe, the set of extreme functions turns out to have a very complicated mathematical structure, as several extreme functions are known that exhibit a somewhat pathological behavior. In this paper we show that if some smoothness assumption is imposed on an extreme function $$\pi $$, then $$\pi $$ is necessarily piecewise linear. More precisely, we show that if a continuous extreme function for the Gomory–Johnson one-dimensional infinite group relaxation is a piecewise $${\mathcal {C}}^2$$ function, then it is a piecewise linear function.

This paper investigates the performance of current-mode chaotic neural networks that are optimized for travelling salesman problem (TSP). Piece-wise linear (PWL) functions used as the output functions in chaotic neurons are found to ease the design of neural network circuits. Three different PWL output functions are compared by solving 10-city TSP. Simulation results showed excellent performance of the chaotic neural networks with PWL output function. The design parameters to implement the PWL output function suitable for TSP chaotic neural networks are obtained.

The paper studies a second order nonlinear differential equation whose right hand side is a piecewise linear function. It proves the coexistence of a countably set of periodic solutions and an uncountable set of bounded non-periodic solutions. The Weierstrass approximation theorem is applied so that the piecewise linear function can be approximated by a polynomial on the finite interval. The result can be also used to explain the chaos on some smooth nonlinear dynamical systems.

The problem of fitting continuous piecewise linear (PWL) functions to discrete data has applications in pattern recognition and engineering, amongst many other fields. To find an optimal PWL function, the positioning of the breakpoints connecting adjacent linear segments must not be constrained and should be allowed to be placed freely. Although the univariate PWL fitting problem has often been approached from a global optimisation perspective, recently, two mixed-integer linear programming approaches have been presented that solve for optimal PWL functions. In this paper, we compare the two approaches: the first was presented by Rebennack and Krasko [Rebennack S, Krasko V (2020) Piecewise linear function fitting via mixed-integer linear programming. INFORMS J. Comput. 32(2):507–530] and the second by Kong and Maravelias [Kong L, Maravelias CT (2020) On the derivation of continuous piecewise linear approximating functions. INFORMS J. Comput. 32(3):531–546]. Both formulations are similar in that they use binary variables and logical implications modelled by big-[Formula: see text] constructs to ensure the continuity of the PWL function, yet the former model uses fewer binary variables. We present experimental results comparing the time taken to find optimal PWL functions with differing numbers of breakpoints across 10 data sets for three different objective functions. Although neither of the two formulations is superior on all data sets, the presented computational results suggest that the formulation presented by Rebennack and Krasko is faster. This might be explained by the fact that it contains fewer complicating binary variables and sparser constraints. Summary of Contribution: This paper presents a comparison of the mixed-integer linear programming models presented in two recent studies published in the INFORMS Journal on Computing. Because of the similarity of the formulations of the two models, it is not clear which one is preferable. We present a detailed comparison of the two formulations, including a series of comparative experimental results across 10 data sets that appeared across both papers. We hope that our results will allow readers to take an objective view as to which implementation they should use.

In this paper we apply one of the main results from the theory of noninvertible maps to predict the oscillations amplitude of a chaotic attractor, using only the lines where the piece-wise linear (PWL) map is not differentiable, their first iterates (called critical lines or curves), and their finite-rank iterates. This approach is also valid for smooth differentiable noninvertible maps, where the critical lines are defined as the first iterates of the set of points for which the Jacobian determinant of the map cancels. Moreover, a novel bifurcation encountered in the case of PWL map is presented: chaotic orbit arising from the collision of a typical bifurcation for smooth maps (the Neimark-Hopf, or center bifurcation) with the bifurcation typical only for piece-wise smooth and non differentiable maps (the border-collision bifurcation). Finally, it is shown that this novel bifurcation can give birth to two (or more) chaotic attractors, and the conditions allowing to predict the number of chaotic attractors which could coexist are proposed and discussed in the context of possible applications.

Single Electron Transistor (SET) is a nanoelectronic device that operates under the controlled mode of tunneled individual electrons. In this paper, a comparative analysis was performed employing SET based D-Flip flop with conventional logic D-flip flop. SET is eminent nanoscale devices that have low power dissipation, high speed and performance. The flip flop design was simulated using SIMON simulator and the stability of its operation was analyzed applying the Monte-Carlo method that represented stability with low power dissipation and matched the functionality of traditional CMOS devices.

A model of angiogenesis by hybrid systems with delay on the piecewise constant part

A set of piecewise-linear (PL) basis functions for signal or functional decomposition is introduced. These basis functions provide a PL approximation to the signal and an a priori determination of the required number for a finite term expansion to achieve a certain pointwise approximation error. Moreover, the expansion coefficients are linear combinations of samples of the function to be expanded and are virtually trivial to determine.