Modified Bit-Flipping Decoding of Low-Density Parity-Check Codes

Recently, in multi-way relay systems employing physical-layer network coding (PNC), channel condition-based pair selection for pairwise information exchange has drawn increased attention as it provides improved performance over the alternative approaches such as round-robin scheduling of node pairs. With pairwise information exchange, there is additional time diversity available due to transmission of the same coded information block of most of the nodes twice in two adjacent time slots. This additional time diversity can be exploited to further enhance the system performance by means of joint channel decoding-network coding. To this end, a joint belief propagation (BP)-based channel decoding-network coding algorithm was proposed by us in [9] for the relay node of low density parity check (LDPC)-coded multi-way relay systems. Even though the algorithm of [9] offers much superior performance over separate channel decoding, it is highly computational expensive and may not be suitable for applications in wireless sensor networks. Alternatively, bit-flipping (BF)-based LDPC decoding can be adopted at much lower computational complexity. In this paper, we develop a low complexity joint bit-flipping (BF)-based channel decoding and network coding algorithm for LDPC-based multi-way relay systems. The BER performance of the proposed algorithm is investigated using computer simulation for two commonly used LDPC codes. The simulation results demonstrate that superior BER performance can be achieved using the proposed joint decoding algorithm over separate and independent bit-flipping-based LDPC channel decoding at the relay. The simulation results also verify that our proposed algorithm is capable of harnessing the aforesaid additional time diversity available. Though the performance of the proposed joint decoding algorithm is inferior to the BP-based algorithm of [9], due to its low computationally complexity, this algorithm may be appealing for applications in relay nodes with low computational capabilities and memory constraints.

Low-density parity-check (LDPC) codes are promising for low code rate applications, however its competitiveness over BCH codes in the high code rate region is not well studied. In this work, we compare the Euclidean geometry (EG) LDPC and BCH codes of the length 1,023, 4,095, and 16,383 that have the code rates of 0.75~0.85. Hard-decision input data are applied to both decoders, and the EG-LDPC codes are decoded using the layered bit-flipping (BF) algorithm. Since the number of needed iterations for LDPC decoding depends on the channel condition, both decoders are designed to have the similar minimum throughput. Not only error performance but also hardware complexity and power consumption of these decoders are compared.

Low-density parity-check (LDPC) codes are predominantly used in many energy scavenging devices, data centres, and communication devices. In this work, the authors propose a high-throughput parallel bit-flipping (BF) decoder using multithreshold BF algorithm. The decoder is endowed with features including low interconnect complexity, simpler computations, and high throughput. The decoder has been synthesised in 65 nm technology for (273, 191) and (1023, 781) finite-geometry LDPC (FG-LDPC) codes. These decoders require an area of 0 . 1 and 0 . 45 mm 2 , and they achieve an average throughput of 147 . 57 and 268 . 5 Gbps and energy efficiency of 0 . 92 and 0 . 91 pJ/bit for (273, 191) and (1023, 781) FG-LDPC codes, respectively. Compared to the state-of-the-art design, the proposed designs offer 4 . 5 times higher normalised throughput.

In this paper a new decoding algorithm for low density parity check (LDPC) codes based on bit flipping (BF) is proposed. In the proposed algorithm, the BF criterion benefits the data correlation between the decoded and received signal in current and previous stages. The proposed algorithm also degrades the decoding probability of one code word to another one in the same codebook. Simulation results confirm our theoretical formulation and show a good enhancement in code error rate and bit error rate of the proposed decoding algorithm compared to the conventional ones.

Based on decoding performance, complexity and latency of finite-geometry low-density parity-check (LDPC) codes, an efficient decoding algorithm is proposed. The algorithm is a hybrid bit-flipping (BF)/majority-logic (MLG) algorithm. In the algorithm, there are two stages. At the first stage, a code is decoded with bit-flipping (BF) with a small fixed number of iterations. Then the output from bit-flipping (BF) decoder is decoded by majority-logic (MLG) decoding. And in bit-flipping (BF) decoding, a new method is used to find the least reliable position. In the hybrid algorithm, there aren't real operations. Simulation results show that the algorithm provides 0.3dB coding gain over weight bit-flipping (WBF) decoding, and within 1 dB away from sum-product algorithm (SPA) decoding.

Low-density parity-check (LDPC) codes have been widely considered as error-correcting codes for next generation communication systems. A good LDPC decoder design requires both implementation friendly LDPC codes and efficient decoder architectures. The quality of LDPC code is crucial in determining the coding gain and implementation complexity of LDPC hardware decoders. This paper presented a genetic algorithm (GA) based LDPC code search algorithm with hardware considerations. Regular quasi-cyclic LDPC codes are used due to its friendliness to hardware implementation. Our hardware architecture design schedules pipeline LDPC decoding operation to boost the hardware utilization efficiency (HUE) of LDPC decoder. A LDPC decoder with a block size of 12288 is implemented in FPGA to validate our code and architecture design.

RRWBF (Reliability ratio based weighted bit-flipping) algorithm is one of the best hard decision decoding algorithms in performance. Recently several modifications are done to this technique either to improve performance or to lower the complexity. The IERRWBF (Implementation efficient reliability ratio based weighted bit-flipping) is developed targeting decreasing processing time of the decoding process. Low Complex IERRWBF (Low complex implementation efficient reliability ratio based weighted bit-flipping) algorithm is one of the latest algorithms targeting lowering decoding complexity, by decreasing number of iterations required to decode received code words and to solve the problem faced by IERRWBF which is the exponential increase in complexity as maximum number of iterations increases. In this paper we are targeting improving the performance of recent developed algorithm named Low Complex IERRWBF by adding a bootstrap step to the decoding technique which leads to increase in reliability of received bits then the number of decoded bits will be increased leading to improvement in performance.

Low-density parity-check (LDPC) codes have been chosen for the fifth-generation (5G) new radio (NR) enhanced Mobile Broad Band (eMBB) data channel. Since NR LDPC codes puncture the first two block columns of the parity-check matrix, the decoding complexity is reduced, but it slows down the convergence rate. In this letter, we propose a fixed schedule that decodes the layers with the least-punctured edges and those with the highest-degree (LPHD), which has much faster convergence speed than conventional schemes. The fixed scheduling schemes cannot take full advantage of the dynamic changes of decoding messages. As a result, the residual-based layered belief propagation (RB-LBP) is proposed to rearrange the layers dynamically among different iterations. Compared with some informed dynamic scheduling (IDS) strategies, RB-LBP reduces the decoding complexity with slight performance loss.

Both polar code and Low-Density Parity-Check (LDPC) code have been adopted in 3GPP eMBB scenario. Some scholars have proposed a serial concatenation structure combining these two codes. However, the inner code needs to add redundant bits to protect the redundant bits of the outer code in the serial concatenation. In this paper, we propose a parallel concatenation code combining polar code and LDPC code on the AWGN channel, which does not distinguish the inner code from the outer code. In the proposed concatenated structure, the BP algorithm is used to decode polar code, and the output soft information of BP decoder is logarithmically processed before LDPC decoding. According to the simulation results, compared with the serial concatenated code with the same code rate and code length, the parallel concatenated code has better BER(Bit-Error-Rate) performance.

Turbo codes are attractive compared with Low Density Parity Check (LDPC) codes for Forward Error Correction (FEC) applications mainly due to their superior performance, especially at low Signal-to-Noise Ratio (SNR) such as are common in Powerline channels. For example, IEEE 1901-FFT PHY used the Turbo coding scheme defined in the HomePlug AV standards. However, patent fees are usually required for each turbo-code enabled manufactured device. The objective of this paper is to examine whether unlicensed LDPC codes, with optimized choices of block lengths, could be a viable alternative for future Powerline Communications (PLC) applications. The paper shows that the performance of the LDPC codes can approximate that of the Turbo codes with higher block lengths, on channels with typical and realistic PLC characteristics. The paper also shows that the additional complexity associated with this increase in block length can be mitigated by the use of Quasi-Cyclic LDPC (QC-LDPC) codes.

Low Density Parity Check (LDPC) codes have capacity-approaching performance over several channels of interest. In practice, for good block-error rate performance, the girth of the Tanner graph of an LDPC code needs to be as high as possible. In theory, to show that block-error rate approaches zero for increasing block-lengths, the girth of the Tanner graph sequence needs to tend to infinity with block-length. To meet these requirements, we construct sequences of large-girth irregular LDPC codes for a given degree-distribution pair (DDP) by applying a general node splitting algorithm on large girth graphs. The obtained Tanner graph meets the required DDP up to a suitable approximation. By optimizing the node-splitting method and using suitable large-girth graphs, we show code constructions with smaller block length for the same girth, when compared to previous constructions. Similar gains in block length are observed in the construction of sequences of large-girth protograph LDPC codes. Simulations, over a binary erasure channel, confirm the gains in block-error rate obtained by the large girth construction.

Big data storage demands larger cluster. The increasing size of the cluster may lead to failures of larger number of nodes. To provide reliable big data storage, replications are not cost-effective and does not provide a robust solution to prevent data loss. Traditional erasure codes applied in the RAID system such as Reed-Solomon (R-S) based solutions have limitations in providing high reliability. This is because higher reliability requires erasure codes with larger size. The computational cost of the R-S codes increase quadratically with the number of failures the R-S codes can tolerate for the same redundancy rate. It has been shown that Low Density Parity Check (LDPC) codes have lower computational cost and repair network traffic compared with R-S based solutions. Unfortunately, there does not exist a construction method for LDPC codes with larger size to control the computational cost and repair traffic. In this paper, a novel method is proposed to construct a family of LDPC codes - expanCodes with expandable sizes. The proposed expanCodes allows the encoding and decoding complexity remain unchanged with the increase of the size of the LDPC codes. As a result, increased reliability can be achieved without additional computation and repair traffic. The proposed expanCodes is integrated with the Hadoop system. Simulations show that more than 29% decrease in terms of encoding and decoding latency compared with R-S based solutions.

In this paper, we propose a concatenated code by combining a Recursive Systematic Convolutional (RSC) code with a Low-Density Parity-Check (LDPC) code. The proposed concatenated code is encoded in parallel by an RSC encoder and an LDPC encoder without interleavers between them. When decoding the proposed concatenated code, the information bits are decoded by two decoding algorithms, and soft information is exchanged between the RSC decoder and the LDPC decoder. This allows for the elimination of wrong codewords output by each decoder. The use of an LDPC code allows us to halt the decoding process when the valid codeword is obtained. We evaluate the error rate performance of the proposed concatenated code by computer simulations. We show that the proposed concatenated code does not have a high error floor, and achieves better BLock Error Rate (BLER) performance than either conventional LDPC codes or conventional turbo codes in the high Eb/No region. We also show that since the proposed concatenated code can correct wrong codewords output by each decoder, it achieves better BLER than the regular LDPC code at the same Bit Error Rate (BER).

With increasing demand of low complexity, higher performance systems ITU adopted Wi-Fi and Wi-Max as one of the IMT 2000 Technologies. Wi-Fi and Wi-Max technologies are major global cellular wireless standards. IEEE 802.16e standards use LDPC (Low Density Parity Check) based SFN (Single Frequency Network) networks. These codes were introduced in 1962 by Gallager. LDPC codes for Wi-max and Wi-Fi is based on the set of one or more fundamental LDPC codes, each of which is systematic linear block codes. These codes can accommodate various code rates and packet sizes. LDPC with the help of high frequency powerful processors is error correcting codes which allows transmission at rates in close proximity to Shannon's limit for large block length. With this paper authors are describing various LDPC codes with low complexity and high performance used for Wi-Fi and Wi-max technologies.

Summary form only given. The ultimate performance limit or threshold of low-density parity-check (LDPC) codes is close to capacity over various memoryless channels (S.-Y. Chung, IEEE Trans. Info. Theory, vol. 47, pp. 657-670, 2001). Since the capacity of binary-input partial response (PR) channels is unknown, we estimate the capacity by calculating the threshold of capacity-approaching LDPC codes over these channels. We assume a BCJR equalizer for the channel and a sum-product message-passing decoder for the LDPC code. We also assume that the log-likelihood ratios (LLRs) in the channel BCJR and the LDPC decoder are Gaussian. We use our results to guide the design of decoder schedules that minimize the number of computationally expensive BCJR steps. The threshold calculation method can be used to optimize the left and right degree sequences of the LDPC code factor graph, using fast linear programming methods, to provide better thresholds than regular codes.