Modular construction of model partitioning processes for parallel logic simulation

Parallelization following the replicated worker principle can significantly accelerate functional logic simulation of microprocessor structures. Successful application of this method strongly depends on circuit model partitioning. We have developed a hierarchical partitioning strategy with prepartitioning and main partitioning as core phases that appear as bottom-up cone clustering. Cones can be seen as special areas of combinational logic which have the ability to directly influence storing or output elements of a circuit model under consideration. We describe and compare three of our cone clustering techniques which are based on a formal model of parallel logic simulation. Experimental results are given with respect to IBM processor structures ranging in their size from several hundred thousand to several million basic elements at a mixture of register-transfer- and gate level.

A new logic simulator called THEMIS (TM) Logic Simulator for the design of LSI, VLSI and PCBs is described. THEMIS supports design verification and test development from initial specification in behavioral and RTL languages to analysis of the final layout at the gate and switch level. To allow the simulation of an entire system or check the correctness of a single circuit, the different modeling techniques can be easily intermixed. THEMIS is a highly interactive simulator that minimizes a hardware engineer's time and effort to debug logic. This paper gives an overview of THEMIS and its use by design engineers.

Logic simulation techniques that reduce both preprocessing time and execution time of unit delay logic simulation are described. Compiled code implementation techniques using a threaded code organization are applied to the event-driven logic simulation algorithm. Simulation speed is increased by a factor of tip to 10 by this technique compared to conventional event-driven simulation. The technique is then extended to hierarchical simulation, in which a fan-out procedure and simulation procedure are generated for each unique module. Hierarchical simulation reduces preprocessing time and allows the recompilation of only those modules that are modified. The simulator uses a portable machine model in which an architecture file describes the target machine. The simulator can be quickly ported to new machines by defining the architecture, while still obtaining high performance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

With the increasing complexity of communication infrastructures in the automotive domain, approaches for modeling architectures at a high abstraction level have become mandatory to assist designers in the development process of such networked embedded systems. Simulation of architecture models, early in the design process, is also necessary to detect and fix errors and performance issues. In this context, transaction level modeling approaches, supported by languages like SystemC, represent promising solutions to allow performances of networked architectures to be assessed with a good compromise between accuracy and simulation speed. This article presents the application of a simulation-based approach for performance evaluation of a networked embedded system inspired by the automotive domain. The presented modeling approach is defined to efficiently capture the characteristics of architectures for real-time image processing applications. The originality of this paper concerns the considered case study which corresponds to the modeling of a video transmission system made of three electronic controller units and based on a specific power line communication protocol. Compared with traditional communication protocols used in the automotive domain, power line communication is considered here to improve integration of advanced real-time image processing applications. The created model incorporates the description of the different communication layers involved in the studied distributed architecture. Simulation of the model allows evaluating time properties of the architecture according to the various system parameters. Furthermore, the memory cost inferred is also evaluated. Architecture parameters can then be correctly tuned to fully meet the expected requirements.

PurposeIncreasingly complex and sophisticated VLSI design, coupled with shrinking design cycles, requires shorter verification time and efficient debug method. Logic simulation provides SoC verification with full controllability and observability, but it suffers from very slow simulation speed for complex design. Using hardware emulation such as FPGA can have higher simulation speed. However, it is very hard to debug due to its poor visibility. SOC HW/SW co‐verification technique seems to draw a balance, but Design Under Test (DUT) still resides in FPGA and remains hard for debugging. The purpose of this paper is to study a run‐time RTL debugging methodology for a FPGA‐based co‐verification system.Design/methodology/approachThe debugging tools are embedded in HDL simulator using Verilog VPI callback, so signals of testbench and internal nodes of DUT can be observed in a single waveform and updated as simulation runs, making debugging more efficient. The proposed debugging method connects internal nodes directly to a PCI‐extended bus, instead of inserting extra scan‐chain logic, so the overhead for area is reduced.FindingsThis method provides internal nodes probing on an event‐driven co‐verification platform and achieves full observability for DUT. The experiment shows that, compared with a similar method, the area overhead for debug logic is reduced by 30‐50 per cent and compile time is shortened by 40‐70 per cent.Originality/valueThe proposed debugging technique achieves 100 per cent observability and can be applied to both RTL and gate‐level verification. The debugging tool is embedded into HDL simulator using Verilog VPI callback, so DUT signals are displayed together with testbench signals in the same waveform viewer. New value of DUT signal is read from FPGA whenever it changes, which allows run‐time debug.

The problem of partitioning mechanical assembly processes to increase throughput and reduce costs is discussed. A partitioning model which takes into account constraints such as precedence relations while maximizing the efficiency or performance is described. A hierarchical portioning method, where several different criteria are used in the partitioning process, is also discussed. >

The push towards faster, denser VLSI device structures and eventually to ULSI devices means ever-decreasing design rules for IC manufacturers. In order to define patterns on silicon and gallium arsenide substrates with feature sizes of 0.25 microns, lithography, metallization, and electronic materials processing techniques will be pushed beyond current limitations. Of these technologies, lithography in the sub-0.5 micron region appears to be the main obstacle yet to be overcome. As deep-UV optical systems become more expensive and the useful field sized decrease in the attempt to achieve finer resolutions, the question of whether to switch to an alternate lithographic method becomes imminent. X-ray lithography is the leading candidate. In this paper, the question of whether x-ray lithography is economically superior to optical lithography and the cost-effectiveness of x-ray lithography are addressed. Also, the question of how x-ray lithography can be performed in a production environment is considered. First shown is that more elaborate optical systems are simply not going to match x-ray proximity system in terms of resolution because of the need to use exotic lens materials or complicated and ever finer reflection systems, none of which can correct for diffraction effects, yet must be corrected for every other aberration. The economic superiority of a synchrotron-based x- ray lithography beamline is demonstrated in a production facility using a processing-cost model based on Shinji Okazaki's cost-per-bit model. Considered, as well, is the strong possibility that exists for the use of an optically based production line which would use an anode or plasma x-ray stepper to define only the smallest geometries, such as the gate level on a DRAM chip. It is shown that it is unlikely, even pushing the limits of materials and optics, that deep-UV systems will be able to define patterns below 0.35 microns in a production environment. X-ray lithography systems could define 0.20 micron patterns in a production environment with a yield that promised to be better than that of optical systems.

&lt;div class="section abstract"&gt;&lt;div class="htmlview paragraph"&gt;Battery Management System (BMS) design is a complex task requiring sophisticated models that mimic the electrochemical behavior of the battery cell under a variety of operating conditions. Equivalent circuits are well-suited for this task because they offer a balance between fidelity and simulation speed, their parameters reflect direct experimental observations, and they are scalable. Scalability is particularly important at the real time simulation stage, where a model of the battery pack runs on a real-time simulator that is physically connected to the peripheral hardware in charge of monitoring and control. With modern battery systems comprising hundreds of cells, it is important to employ a modeling and simulation approach that is capable of handling numerous simultaneous instances of the basic unit cell while maintaining real time performance.&lt;/div&gt;&lt;div class="htmlview paragraph"&gt;In previous publications we presented a technique for the creation of a battery cell model that contains the electrochemical fingerprints of a battery cell based on equivalent circuit model fitting to experimental data. In this work we extend our previous model to represent a battery pack, featuring cell creation, placement, and connection using automation scripts, thus facilitating the design of packs of arbitrary size and electrical topology. In addition, we present an assessment of model partitioning schemes for real time execution on multicore targets to ensure efficient use of hardware resources, a balanced computational load, and a study of the potential impact of the calculation latencies inherent to distributed systems on solver accuracy. Prior to C code generation for real time execution, a model profiler assesses the model partitioning and helps determine the multicore configuration that results in the lowest average turnaround time, the time elapsed between task start and finish.&lt;/div&gt;&lt;div class="htmlview paragraph"&gt;The resulting model is useful in the generation of multiple operating scenarios of interest in the design of charging, balancing, and safety related procedures.&lt;/div&gt;&lt;/div&gt;

Coverage path planning is one of the important issues for robot mowers, which brings great convenience to our life. In this paper, hierarchical partitioning strategy is employed to fulfill robot's environment modeling and the double heuristic optimization algorithms have been adopted to plan optimal coverage paths. Ant Colony Optimization (ACO) is used for global path planning in the upper layer, and Tabu Search (TS) is used for local coverage planning in the lower layer. Finally, simulation experiments are carried out and the results show the proposed method obtains satisfactory coverage path planning.

Multiple-delay logic simulation algorithms developed for the microprogrammable accelerator for rapid simulations (MARS) hardware simulator are discussed. In particular, timing-analysis algorithms for event cancellations, spike and race analyses, and oscillation detection are described. It is shown how a reconfigurable set of processors, called processing elements (PEs), can be arranged in a pipelined configuration to implement these algorithms. The algorithms operate within the partitioned-memory, message-passing architecture of MARS. Three logic simulators-two multiple delay and one unit delay-have been implemented using slightly different configuration of the available PEs. In these simulators, VLSI chips are modeled at the gate level with accurate rise/fall delays assigned to each logic primitive. On-chip memory blocks are modeled functionally and are integrated into the simulation framework. The MARS hardware simulator has been tested on many VLSI chip designs and has demonstrated a speed improvement of about 50 times that of an Amdahl 5870 system running a production-quality software simulator while retaining the accuracy of simulations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Mixed analog and digital mode simulators have been available for accurate /spl alpha/-particle-induced transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. In this paper, we describe a gate-level transient fault simulation environment which has been developed based on realistic fault models. Although the environment was developed for /spl alpha/-particle-induced transient faults, the methodology can be used for any transient fault which can be modeled as a transient pulse of some width. The simulation environment uses a gate level timing fault simulator as well as a zero-delay parallel fault simulator. The timing fault simulator uses logic level models of the actual transient fault phenomenon and latch operation to accurately propagate the fault effects to the latch outputs, after which point the zero-delay parallel fault simulator is used to speed up the simulation without any loss in accuracy. The environment is demonstrated on a set of ISCAS-89 sequential benchmark circuits.

Sorption phenomena of very hydrophobic compounds (VHOCs, log K(OW) > 5) on dissolved humic organic matter (DOM) are overwhelmingly based on partitioning processes. In this respect, DOM is very similar to "rubbery" soil/sediment OM. To exclude system adsorption effects, the DOM sorption coefficients (K(DOM)) of VHOCs were determined using a dynamic approach based on the VHOCs' aqueous solubility enhancement in the presence of DOM. Partition coefficients are strongly correlated to the analytes' Kow across the alkane, PAH, and PCB groups under study. These three "families" are regarded to be good models of hydrophobic partitioning. On the basis of a uniform one-parameter concept characterizing sorption on amorphous polymers, Hildebrand solubility parameters of amorphous polymeric sorbents, including DOM, and of sorbates can be calculated on the basis of partition coefficients. Likewise, partition coefficients can be estimated using Hildebrand solubility parameters. Literature-based partition coefficients on DOM fit very well in this universal one-parameter concept. On using our own sorption data of PAHs, PCBs, and alkanes on DOM, an almost identical solubility parameter for the DOM polymer under study is obtained. The concept is also very useful in understanding both waterborne and airborne bioconcentration processes, which are considered to be partitioning phenomena.

Power reduction is nowadays becoming the first consideration in VLSI design. Low power is one of major concerns in deeply scaled CMOS technologies. There have been many methods in very wide rang to achieve this objective. And the Register-Transfer level (RTL) has become the most effective stage in low power VLSI design, according to the significant power optimization impact and accurate power estimation. In this paper, some respective low power design techniques at RTL are re-investigated at tsmc 45 nanometer CMOS technology. Clock gating (CG) is one of the most widely used and effective technique in RTL low power design. Without the enable signal, bus-specific clock gating (BSC) and threshold-based clock gating (TCG) are considered. Also an improved active-driven optimized bus-specific clock gating (OBSC) is proposed in our laboratory. When the enable signal is taken into account, this paper explains local-explicit clock gating (LECG), enhanced clock gating (ECG), waste-toggle-rate-based (WTR) clock gating and the single comparator-based clock gating (SCCG) techniques. Operand isolation is another useful design technique for reducing the power consumption by blocking some redundant operations. Memory splitting is an effective design solution for low power design as well. These techniques have been experimented by using tsmc 45nm technology library and the proposed low-power RTL techniques are evaluated at gate level with logic synthesis results.

As the VLSI technology grows up, optimization is required to reduce the complexity, area and power of the digital circuits. In order to optimize the hardware requirement of digital combinational circuits, evolutionary techniques need to be enforced at various levels such as gate level and device level. This paper presents an efficient approach for the optimal design of a combinational logic circuit with a reduced gate count in MATLAB platform. The evolutionary optimization technique used is Particle Swarm Optimization with Aging Leader and Challenger (ALC-PSO). The results obtained after optimization of Full Subtractor circuit using ALC-PSO technique are shown to have a less number of gates compared to human design method. Later on that optimized circuit has been analysed by DSCH3.5 and Microwind3.1 VLSI CAD Tool. The results shown in this paper reflects that technology scaling decreases the area, delay and power consumption which are some of the major requirements of today's VLSI design.

Cycle-based simulation at register-transfer- and gate level realized by a Levelized Compiled Code (LCC) technique represents a well established method for functional verification in processor design. Due to rapidly increasing design sizes, simulation acceleration is an important issue. We present a parallel LCC simulation system that has been developed to run on loosely-coupled systems. It comprises three parallel simulators and a complex model partitioning environment. An essential idea of our parallelization approach is to valuate circuit model partitions with respect to the expected parallel simulation run-time and to integrate corresponding cost functions into partitioning algorithms. This is done on the basis of a formal model of parallel LCC simulation. In this paper, we focus on the strong relation between model partitioning and the parallel simulation technique chosen. The components of the simulation system are outlined and experimental results with respect to simulation acceleration are given for IBM processor models of different size.