THEMIS Logic Simulator - A Mix Mode, Multi-Level, Hierarchical, Interactive Digital Circuit Simulator

Logic simulation of complex VLSI models is very time consuming. Simulation speed can be increased by model partitioning and assigning the resulting parts to simulator instances which cooperate over a loosely coupled system. We have developed a distributed framework, parallelMAP, that implements a hierarchical model partitioning strategy. It can serve both as production environment in VLSI design and as an experimental test bed for algorithm development. In this paper, we describe the possibilities that parallelMAP offers for the modular construction of partitioning processes, starting from basic sequential and parallel modules. Experimental experiences refer to IBM processor models comprising from 1.5 x 105 to 2.5 x 106 elements at gate level.

With the publication of the Framework for K-12 Science Education (National Research Council, 2012) and adoption of the Next Generation Science Standards (NGSS), emphasis is now placed on the integration of engineering principles and practices into formal science education. Engineering design allows teachers to effectively blend disciplines and integrate math and science as a means of building student understanding of and skills for engaging in both content areas and appreciation for both content areas (Lehman & Capobianco, 2012). Integration of engineering design into school curricula, however, requires teachers to have content knowledge, pedagogical skills, and resources necessary to promote student learning in math and science through design (Lehman & Capobianco, 2012). Content-focused PD has been found key to improving teacher knowledge of STEM (Wilson, 2013). Pre-college engineering education providers, such as Project Lead The Way (PLTW) and Engineering Is Elementary (EiE), offer comprehensive curricula and professional development opportunities in engineering education. These programs are high quality and provide an entry point into engineering education for K12 teachers; however, the engineering design exercises are prescriptive and vary in the degree to which they explicitly address the science standards inherent to the design problem. In addition, most K12 educators often struggle to adapt or to create from scratch design experiences for their classrooms. Therefore, there is a need for professional development that provides K12 educators with grade-band appropriate content knowledge in engineering design and makes explicit the process creating or adapting classroom-based engineering design experiences. This study data presents a from a three-year effort to develop and implement a weeklong professional development institutes for K12 teachers focused on engineering design. The effort, funded through a state grant, was executed as a partnership between the colleges of education and engineering at a mid-sized state university. In Year 1 (Summer 2015), course learning objectives were finalized as: (1) developing a working knowledge of the engineering design process (EDP); (2) differentiating between engineering design and “making”; (3) understand how the EDP aligns with NGSS; (4) apply different modeling and prototyping techniques; (5) independently creating engineering problem statements applicable to particular grades in K-12; and (6) developing pedagogical techniques for successfully implementing classroom-based design challenges. Year 2 (Summer 2016) included refinement of teacher deliverables to include: (1) self-generated database of engineering design lesson plans, stratified by grade band and NAE Engineering Grand Challenge areas; (2) functional first-generation prototype from established design challenges; (3) lesson scaffolding and exemplar student work for design challenges; and (4) participation in peer-evaluated design critiques. Summative program evaluation was performed in Year 3 with only minor changes in the course content from prior years. A total of 36 teachers participated in the five-day workshop and were clustered in working groups by grade band (K-2, 3-5, 6-8, and 9-12). Summative evaluation included pre- and post-workshop surveys, observation and interviews, and in-classroom follow up during in Fall 2017. Short-term outcome measures include pre-post changes in teacher self-efficacy related to core content, hands-on prototyping, and the engineering design process. Longer term measures include teachers’ implementation of a novel or adapted engineering design lessons in their classrooms and evaluation of the alignment and quality of these exercises through student deliverables. Short-term measures showed gains in most measures of self-efficacy; in-classroom follow-up is presently underway and will be presented in this study. Adoption of NGSS presents an opportunity for the engineering profession to expand and diversify its talent pipeline; however, this opportunity will only be realized if K12 teachers are well-prepared to deliver high quality, grade-band appropriate engineering experiences in their own classrooms. The professional development curriculum created in this study may be used as a model to empower teachers to develop and adapt NGSS-aligned curriculum.

The development of high speed, large capacity hardware systems for logic simulation makes boolean comparison of logic networks feasible for designs of practical importance. Boolean comparison provides a complete check of functional equivalence of two logic networks and is a valuable tool in design verification. This paper describes virtual logic that controls the boolean comparison process and provides large reductions in the required number of test cases for many practical design problems. The virtual logic is simulated by the logic simulation system at the same time as the two models are simulated for test cases. The virtual logic has the task of generating new test cases such that the entire input space is covered but minimizing the number of test vectors required. Multivalued logic simulation and other techniques are used to achieve the reductions. Since the entire boolean comparison task is completed without assistance of a general purpose host system the usual communication overhead is avoided. The techniques described are suitable for high speed logic simulators. The simulation system for the work described here was the Engineering Verification Engine (EVE) developed by IBM but other simulation systems provide similar capability.

Parallelization following the replicated worker principle can significantly accelerate functional logic simulation of microprocessor structures. Successful application of this method strongly depends on circuit model partitioning. We have developed a hierarchical partitioning strategy with prepartitioning and main partitioning as core phases that appear as bottom-up cone clustering. Cones can be seen as special areas of combinational logic which have the ability to directly influence storing or output elements of a circuit model under consideration. We describe and compare three of our cone clustering techniques which are based on a formal model of parallel logic simulation. Experimental results are given with respect to IBM processor structures ranging in their size from several hundred thousand to several million basic elements at a mixture of register-transfer- and gate level.

Multiple-delay logic simulation algorithms developed for the microprogrammable accelerator for rapid simulations (MARS) hardware simulator are discussed. In particular, timing-analysis algorithms for event cancellations, spike and race analyses, and oscillation detection are described. It is shown how a reconfigurable set of processors, called processing elements (PEs), can be arranged in a pipelined configuration to implement these algorithms. The algorithms operate within the partitioned-memory, message-passing architecture of MARS. Three logic simulators-two multiple delay and one unit delay-have been implemented using slightly different configuration of the available PEs. In these simulators, VLSI chips are modeled at the gate level with accurate rise/fall delays assigned to each logic primitive. On-chip memory blocks are modeled functionally and are integrated into the simulation framework. The MARS hardware simulator has been tested on many VLSI chip designs and has demonstrated a speed improvement of about 50 times that of an Amdahl 5870 system running a production-quality software simulator while retaining the accuracy of simulations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In recent years, the verification of digital designs has become one of the most challenging, time consuming and critical tasks in the entire hardware development process. Within this area, the vast majority of the verification effort in industry relies on logic simulation tools. However, logic simulators deliver limited performance when faced with vastly complex modern systems, especially synthesized netlists. The consequences are poor design coverage, delayed product releases and bugs that escape into silicon. Thus, we developed a novel GPU-accelerated logic simulator, called GCS, optimized for large structural netlists. By leveraging the vast parallelism offered by GP-GPUs and a novel netlist balancing algorithm tuned for the target architecture, we can attain an order-of-magnitude performance improvement on average over commercial logic simulators, and simulate large industrial-size designs, such as the OpenSPARC processor core design.

Almost a decade has passed since the OMG has issued the Model Driven Architecture (MDA) initiative. It soon became obvious that raising the level of abstraction in development and reasoning at the model level would help in asking the right questions at the right time. Based on a concrete problem, we discuss four alternative solutions to a multi-language system design problem. These solutions use a traditional approach, a technique based on modeling, a domain-specific approach, and a mix of modeling and domain-specific techniques, respectively. The solutions depend on the problem, but they are representative for the situations we encounter in practice, therefore giving us a good basis for a larger discussion on the appropriateness of using modeling techniques and on the place of MDA in current software engineering practice and design.

A propulsion dynamics investigation of a single-screw powered ship, driven by two gas turbines in a combined gas and gas (COGAG) arrangement is presented. Distributed-lumped (hybrid) modelling techniques are applied to the propulsion drive-train consisting of two prime movers, a primary drive shaft, a reduction gearbox, a secondary drive shaft and a propeller. The study in this paper, unlike earlier studies, does not lump the drive-train components as discussed by Rubis [1] into analytically simple but unrepresentative pointwise models. By way of contrast, modelling and simulation techniques for distributed-lumped systems are presented herein, enabling the torsional vibration and stress analysis of the long drive shafts to be investigated with accuracy. As a result of this a torque control scheme can be derived for fuel flow regulation purposes, enabling superior speed and shaft torque control to be achieved. The results presented show the simulated dynamic responses associated with the propulsion unit, shaft and propeller following fuel flow changes.

Graphics Processing Units (GPUs) are gaining popularity for parallelization of general purpose applications. GPUs are massively parallel processors with huge performance in a small and readily available package. At the same time, the emergence of general purpose programming environments for GPUs such as CUDA shorten the learning curve of GPU programming. We present a GPU-based parallelization of logic simulation algorithm for electronic designs. Logic simulation is a crucial component of verification of electronic designs that allows one to check whether the design behaves according to the specifications. Verification of electronic designs consumes more than 60% of the overall design cycle. Any attempts to speedup the verification process (and logic simulation) results in great savings and shorter time-to-market. We develop a parallel cycle-based logic simulation algorithm that uses And Inverter Graphs (AIGs) as design representations and exploits the massively parallel GPU architecture. We demonstrate several orders of speedups on benchmarks using our system.

: Mathematical modeling is becoming a vital tool in engineering design. These models have been used to provide decision support to designers of systems characterized by many design choices. However, for the design of complex systems, these models become too large and cumbersome to be of significant value. As a result, research has progressed in the decomposition of the design problem. A decision support system, serving as a computer-based aid for engineers designing weapon systems, must integrate procedures dealing with designing for producibility and designing for supportability with those dealing with designing for performance cost and schedule (ULCE Implementation Plan, 1987). One of the characteristics of large weapon system development that causes difficulties in achieving this integration is the hierarchical nature of the design process. Typically, a system is designed in terms of subsystems which are required to meet certain specifications. Problems begin to arise when these specifications cannot be met. Consequently, these design processes may be enhanced by a computer-based system that supports the hierarchical nature of design. This research examines the application of mathematical modeling and knowledge-based system techniques to the development of decision support systems to support engineering design.

Power reduction is nowadays becoming the first consideration in VLSI design. Low power is one of major concerns in deeply scaled CMOS technologies. There have been many methods in very wide rang to achieve this objective. And the Register-Transfer level (RTL) has become the most effective stage in low power VLSI design, according to the significant power optimization impact and accurate power estimation. In this paper, some respective low power design techniques at RTL are re-investigated at tsmc 45 nanometer CMOS technology. Clock gating (CG) is one of the most widely used and effective technique in RTL low power design. Without the enable signal, bus-specific clock gating (BSC) and threshold-based clock gating (TCG) are considered. Also an improved active-driven optimized bus-specific clock gating (OBSC) is proposed in our laboratory. When the enable signal is taken into account, this paper explains local-explicit clock gating (LECG), enhanced clock gating (ECG), waste-toggle-rate-based (WTR) clock gating and the single comparator-based clock gating (SCCG) techniques. Operand isolation is another useful design technique for reducing the power consumption by blocking some redundant operations. Memory splitting is an effective design solution for low power design as well. These techniques have been experimented by using tsmc 45nm technology library and the proposed low-power RTL techniques are evaluated at gate level with logic synthesis results.

As the VLSI technology grows up, optimization is required to reduce the complexity, area and power of the digital circuits. In order to optimize the hardware requirement of digital combinational circuits, evolutionary techniques need to be enforced at various levels such as gate level and device level. This paper presents an efficient approach for the optimal design of a combinational logic circuit with a reduced gate count in MATLAB platform. The evolutionary optimization technique used is Particle Swarm Optimization with Aging Leader and Challenger (ALC-PSO). The results obtained after optimization of Full Subtractor circuit using ALC-PSO technique are shown to have a less number of gates compared to human design method. Later on that optimized circuit has been analysed by DSCH3.5 and Microwind3.1 VLSI CAD Tool. The results shown in this paper reflects that technology scaling decreases the area, delay and power consumption which are some of the major requirements of today's VLSI design.

In this study, the modelling and simulation of chaotic Rossler system has been carried out by using an intelligent system based on neuro-fuzzy modelling technique. Furthermore, the MATLAB simulation of chaotic Rossler system has been carried out for comparison with proposed technique. Structure of the Adaptive Neuro-Fuzzy Inference System (ANFIS) is improved and trained in MATLAB toolbox. A hybrid learning algorithm consists of back-propagation and least-squares estimation is used for training the ANFIS network. Numerical simulations are used in this study. We have used four various data sets for testing the simulation speed of ANFIS and MATLAB. Obtained Results show that the proposed modelling technique has much higher speed and accuracy in comparison with MATLAB simulation. The neuro-fuzzy modelling technique can be simply used in software tools for designing and simulation of the chaotic Rossler system and the other chaotic systems.

Integrating Core Systems Engineering Design Concepts into Traditional Engineering DisciplinesIn this study we describe the integration of core systems engineering design concepts intotraditional mechanical and electrical engineering curriculum at the University of Arkansas atLittle Rock (UALR) undergraduate Systems Engineering program. The program was launched in1999 in response to the industry demands for engineering graduates capable of managingcomplex engineering projects. The program has since graduated over 150 students who areworking in industry (aerospace, defense, manufacturing, design, and consulting), federal andstate government, or attending graduate school. The program curriculum has four broadcomponents: a 35 hour university core that covers basic math and science (11 hours) and generaleducation (24 hours); a 30 hour college core that enhances the math and science preparation witha course in engineering ethics; a 32 systems engineering component that introduces core systemsengineering concepts; and, a 32 hour option component that teaches the mechanical or electricalengineering disciplines. The program is accredited by ABET under general criteria, and plans areunderway to satisfy mechanical and electrical engineering program criteria. Students entering theprogram are introduced to systems engineering core concepts through courses in EngineeringEconomy, DES Modeling and Simulation, Optimization Methods, Decision and Risk Analysis,and Systems Engineering Design and Analysis. Among them, Engineering Economy coversengineering project evaluation and economic decision making. Optimization Methods in SystemsEngineering covers linear and nonlinear methods of engineering design optimization. DESModeling and Simulation covers theory and practice of discrete event simulation modeling.Decision and Risk Analysis covers uncertainty modeling and analytical techniques for rationaldecision making. Systems Engineering Design and Analysis covers the systems engineering life-cycle process, including identification of system requirements, engineering design andarchitecture, system modeling, testing and integration, and system operation and support. The128-hr program culminates in a two-semester Systems Engineering Capstone Design thatemphasizes the multi-disciplinary nature of the program. The students perform functional designin the first semester followed by detailed physical design and testing in the second semester. TheUALR program graduates skilled systems engineers who combine holistic thinking with deepproduct knowledge, strong technical background, effective communication skills, and goodinterpersonal skills.

Design verification via simulation is an important component in the development of digital systems. However, with continuing increases in the capabilities of VLSI systems, the simulation task has become a significant bottleneck in the design process. As a result, researchers are attempting to exploit parallel processing techniques to improve the performance of VLSI logic simulation. This tutorial describes the current state-of-the-art in parallel logic simulation, including parallel simulation techniques, factors that impact simulation performance, performance results to date, and the directions currently being pursued by the research community.