Monolithic 3D-ICs with single crystal silicon layers

Monolithic 3D IC is an emerging technology to continuously satisfy demands for power reduction under challenges posed by traditional device scaling. In this paper, for the first time, we study power benefits of 4-tier monolithic 3D ICs compared with 2-tier monolithic 3D and 2D ICs. We present a tier partitioning methodology that significantly extends the capability of a state-of-the-art flow built for 2-tier monolithic 3D ICs. We develop two complete RTL-to-GDSII design flows to achieve this goal and offer quantitative comparisons. In addition, we study impacts of inter-tier via usage on 2-tier and 4-tier monolithic 3D ICs. Our experiments show that poorly controlled inter-tier via usage results in up to 6.05% degradation in total power savings. Thus, we develop an effective strategy to achieve inter-tier via configurations to optimize power metrics. Experiments show that 4-tier monolithic 3D ICs outperform 2-tier and 2D IC by 15% and 50% in terms of power and 25% and 75% in area under the same performance.

The state-of-the-art Monolithic 3D (M3D) IC design methodologies~\citem3d:Ku-tcad-Compact2D, m3d:Panth-tcad-Shrunk2D use commercial electronic design automation tools built for 2D ICs to implement a pseudo-3D design and split it into two dies that are routed independently to create an M3D design. Therefore, an accurate estimation of 3D wire parasitics at the pseudo-3D stage is important to achieve a well optimized M3D design. In this paper, we present a regression model based on boosted decision tree learning to better predict the 3D wire parasitics (RCs) at the pseudo-3D stage. Our model is trained using individual net features as well as the full-chip design metrics using multiple instantiations of 8 different netlists and is tested on 3 unseen netlists. Compared to the Compact-2D~\citem3d:Ku-tcad-Compact2D flow on its own as the reference pseudo-3D, the addition of our predictive model achieves up to $2.9 \times$ and $1.7 \times$ smaller root mean square error in the resistance and capacitance predictions respectively. On an unseen netlist design, we observe that our model provides 98.6% and 94.6% RC prediction accuracy in 3D and up to $6.4 \times$ smaller total negative slack of the design compared to the result of Compact-2D flow resulting in a more timing-robust M3D IC. This model is not limited to Compact-2D, and can be extended to other pseudo-3D flows.

Monolithic inter-layer vias (MIVs) used in 3D integration technology are much smaller than through-silicon vias (TSVs) used in TSV-based 3D integration. Thus, monolithic 3D integration provides shorter wire length, better performance, and lower power consumption than TSV-based 3D integration. Multi-tier monolithic 3D integration stacks more than two silicon layers, thereby increasing the device density, which reduces the wire length and power consumption and improves performance further than two-tier monolithic 3D integration. Since the size of an MIV is comparable to that of a local via, the wire lengths of multi-tier gate-level monolithic 3D IC layouts are expected to be close to the ideal wire length reduction ratio, for example, 29, 42, and 50 percent for two-, three-, and four-tier designs, respectively. However, it is still unknown whether it would be possible to achieve the ideal wire length reduction ratios by multi-tier gate-level monolithic 3D integration. In this paper, we propose an efficient routing methodology to design multi-tier monolithic 3D ICs. Using the design methodology, we design two- to eight-tier gate-level monolithic 3D IC layouts and thoroughly investigate the wire length characteristics of the layouts. The simulation results show that the proposed routing methodology reduces the wire length by 12 to 53 percent compared to the 2D designs. In addition, the proposed routing methodology builds multi-tier monolithic 3D IC layouts more efficiently than a state-of-the-art methodology with comparable routed wire length.

A new multi-user hybrid surface and bulk micromachining process on silicon-on-insulator (SOI) wafers is discussed. This 13-mask process consists of a doped polysilicon layer for electrical connection and non-critical structures and a single crystal silicon (SCS) layer for excellent optical and mechanical properties in the critical MEMS design. There are 7 masks for doping and etching of the SCS layer. The flexibility and versatility of this process allows for microsystems designs such as actuators, optical gratings, and dimples/anchors on the SCS layer. The MEMS devices fabricated and tested in this paper include thermal actuators, hinges, latches, optical switches, mirrors, and waveguides.

Network-on-chips (NoCs) with traditional regular topologies generally have an average-hop-count increased, polynomially, with the network size. This brief proposes to generate brain-network-inspired (BNI) topologies on monolithic 3D (M3D) ICs, where the average hop count scales up logarithmically, for large-scale systems with tens of thousands of cores. We propose a routability-driven method to generate BNI topologies on M3D ICs with scale-free and small-world properties. Moreover, we present an iterative method to reduce the network diameter using as few tier-crossing routers as possible. The resulting BNI topologies not only have over 50% lower average hop count and lower diameter than traditional regular topologies, but also have shorter total link length than other irregular topologies. The performance is further validated by the cycle-accurate simulation.

Monolithic 3D (M3D) is an emerging technology that enables integration density which is orders of magnitude higher than that offered by through-silicon-vias. In this paper, we demonstrate that a modified 2D placement technique coupled with a post-placement partitioning step is sufficient to produce high-quality M3D placement solutions. We also present a commercial router-based monolithic intertier via insertion methodology that improves the routability of M3D ICs. We demonstrate that, unlike in 2D ICs, the routing supply and demand in M3D ICs are not completely independent of each other. We develop a routing demand model for M3D ICs, and use it to develop an O(N) min-overflow partitioner that enhances routability by off-loading demand from one tier to another. This technique reduces the routed wirelength and the power delay product by up to 7.44% and 4.31%, respectively. This allows a two-tier M3D IC to achieve, on average, 19.9% and 11.8% improvement in routed wirelength and power delay product over 2D, even with reduced metal layer usage.

Smart-Cut ® technology: from 300 mm ultrathin SOI production to advanced engineered substrates

As Moore's law approaches its physical limits, 3D integrated circuit (3D IC) technology has emerged as a crucial way to increase chip integration density. Due to their small size, high carrier mobility, and low power consumption, carbon nanotube field‐effect transistors (CNTFETs) offer a promising way to overcome the limitations imposed by Moore's law. The evolution of ICs and 3D integration technologies for the post‐Moore era, such as chiplets and multilayer stacking are reviewed, and the potential applications and value of CNTFETs in 3D optoelectronics, memory, and monolithic 3D ICs are explored. The prospects of novel device structures like FinFETs and gate‐all‐around FETs are also discussed. CNT 3D ICs have tremendous potential for these applications, but challenges remain in material fabrication, device performance, and 3D structure design. Researchers are actively exploring solutions such as optimizing fabrication processes, developing new materials, and innovative logic design methodologies. Notably, the integration of CNTFETs with chiplet technology promises more efficient and flexible chip design and manufacturing, catering to the future demand for high‐performance, low‐power, and high‐density ICs.

Monolithic three-dimensional (3D) integration enables the most fine-grained integration of transistors by stacking very thin layers and fabricating monolithic inter-layer vias as small as local vias. Thus, monolithic 3D integration is expected to provide a higher degree of wirelength reduction, performance improvement, and power saving. Due to the prospective properties of the monolithic 3D integration technology, research on multilayer monolithic 3D integration that stacks more than two device layers is also ongoing. In this paper, we propose an algorithm that optimizes dynamic power consumption of gate-level monolithic 3D ICs. Under the same timing constraints, our algorithm reduces dynamic power consumption more effectively than a uniform-scaling-based placement algorithm. We also design multi-tier monolithic 3D ICs and show that our algorithm outperforms the uniform-scaling-based placement algorithm by 11.4% on average.

The recent advancement of wafer bonding and monolithic integration technology offers fine-grained 3-D interconnections to face-to-face (F2F) and monolithic 3-D (M3D) ICs. In this article, we propose a full-chip RTL-to-GDSII physical design solution to build commercial-quality two-tier gate-level F2F and M3D ICs. The state-of-the-art flow named shrunk2D (S2D) requires shrinking of standard cells and interconnects by a factor of 50% to fit into the target 3-D footprint of a two-tier design. This, unfortunately, necessitates commercial place/route engines that handle one node smaller geometries, which can be challenging and costly. Our flow named compact-2D (C2D) does not require any geometry shrinking. Instead, C2D implements a 2-D IC with scaled interconnect RC parasitics and contracts the layout to the 3-D integrated circuit footprint. In addition, C2D offers post-tier-partitioning optimization (post-TP opt) which is completely missing in S2D. This additional optimization step is shown to be effective in fixing timing violations caused by inter-tier 3-D routing overhead. Lastly, we present a methodology to reuse the routing result of post-TP opt for the final GDSII generation. Our experimental results show that at iso-performance, C2D offers up to 28.0% power reduction and 15.6% silicon area savings over commercial 2-D ICs without any routing resource overhead.

Photoelectrochemical performance of TiO2 photoanodes: Nanotube versus nanoflake electrodes

Thermal engineering of many nanoscale sensors, actuators, and high-density thermomechanical data storage devices, as well as the self-heating in deep submicron transistors, are largely influenced by thermal conduction in ultrathin silicon layers. The present study measures the lateral thermal conductivity of single-crystal silicon layers of thicknesses 20 and 100 nm at temperatures between 20 and 300 K, using Joule heating and electrical–resistance thermometry in suspended microfabricated structures. The thermal conductivity of the 20 nm thick silicon layer is ∼22 W m−1 K−1, which is nearly an order of magnitude smaller than the bulk value at room temperature. In general, a large reduction in thermal conductivity resulting from phonon–boundary scattering, particularly at low temperatures, is observed. It appears that the classical thermal conductivity theory that accounts for the reduced phonon mean-free paths based on a solution of the Boltzmann transport equation along a layer is able to capture the ballistic, or nonlocal, phonon transport in ultrathin silicon films.

The photoluminescence of single-crystal silicon layers (100) subjected to mechanical processing (grinding and polishing) is investigated. An intense photoluminescence signal at 77 K with a peak at 0.83 eV (1.5 µm) and FWHM=50 meV was observed after annealing at 800°C. The possible origin of this signal is discussed and is tentatively related to dislocations decorated by impurity atoms.

Simulations of the temperature field in silicon-on-insulator (SOI) and strained-Si transistors can benefit from experimental data and modeling of the thin silicon layer thermal conductivity at high temperatures. This paper develops algebraic expressions to account for the reduction in thermal conductivity due to the phonon-boundary scattering for pure and doped silicon layers and presents the experimental data for 50-nm-thick single-crystal silicon layers at high temperatures. The model applies to the temperature range of 300-1000 K for silicon layer thicknesses from 10 nm to 1 mum (and even bulk), which agrees well with the experimental data. In addition, the algebraic model has an excellent agreement with both the experimental data and predictions of thin-film thermal conductivity based on thermal conductivity integral and Boltzmann transport equation. The analytical thermal modeling and ISE-TCAD electrothermal simulations confirm that both the electrical and thermal performances of SOI transistor can be largely affected if the reduced thermal conductivity of the silicon due to phonon boundary scattering is not properly taken into consideration

Vacuum deposition of silicon on corundum