Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs

Monolithic 3D IC is an emerging technology to continuously satisfy demands for power reduction under challenges posed by traditional device scaling. In this paper, for the first time, we study power benefits of 4-tier monolithic 3D ICs compared with 2-tier monolithic 3D and 2D ICs. We present a tier partitioning methodology that significantly extends the capability of a state-of-the-art flow built for 2-tier monolithic 3D ICs. We develop two complete RTL-to-GDSII design flows to achieve this goal and offer quantitative comparisons. In addition, we study impacts of inter-tier via usage on 2-tier and 4-tier monolithic 3D ICs. Our experiments show that poorly controlled inter-tier via usage results in up to 6.05% degradation in total power savings. Thus, we develop an effective strategy to achieve inter-tier via configurations to optimize power metrics. Experiments show that 4-tier monolithic 3D ICs outperform 2-tier and 2D IC by 15% and 50% in terms of power and 25% and 75% in area under the same performance.

The state-of-the-art Monolithic 3D (M3D) IC design methodologies~\citem3d:Ku-tcad-Compact2D, m3d:Panth-tcad-Shrunk2D use commercial electronic design automation tools built for 2D ICs to implement a pseudo-3D design and split it into two dies that are routed independently to create an M3D design. Therefore, an accurate estimation of 3D wire parasitics at the pseudo-3D stage is important to achieve a well optimized M3D design. In this paper, we present a regression model based on boosted decision tree learning to better predict the 3D wire parasitics (RCs) at the pseudo-3D stage. Our model is trained using individual net features as well as the full-chip design metrics using multiple instantiations of 8 different netlists and is tested on 3 unseen netlists. Compared to the Compact-2D~\citem3d:Ku-tcad-Compact2D flow on its own as the reference pseudo-3D, the addition of our predictive model achieves up to $2.9 \times$ and $1.7 \times$ smaller root mean square error in the resistance and capacitance predictions respectively. On an unseen netlist design, we observe that our model provides 98.6% and 94.6% RC prediction accuracy in 3D and up to $6.4 \times$ smaller total negative slack of the design compared to the result of Compact-2D flow resulting in a more timing-robust M3D IC. This model is not limited to Compact-2D, and can be extended to other pseudo-3D flows.

Network-on-chips (NoCs) with traditional regular topologies generally have an average-hop-count increased, polynomially, with the network size. This brief proposes to generate brain-network-inspired (BNI) topologies on monolithic 3D (M3D) ICs, where the average hop count scales up logarithmically, for large-scale systems with tens of thousands of cores. We propose a routability-driven method to generate BNI topologies on M3D ICs with scale-free and small-world properties. Moreover, we present an iterative method to reduce the network diameter using as few tier-crossing routers as possible. The resulting BNI topologies not only have over 50% lower average hop count and lower diameter than traditional regular topologies, but also have shorter total link length than other irregular topologies. The performance is further validated by the cycle-accurate simulation.

Monolithic inter-layer vias (MIVs) used in 3D integration technology are much smaller than through-silicon vias (TSVs) used in TSV-based 3D integration. Thus, monolithic 3D integration provides shorter wire length, better performance, and lower power consumption than TSV-based 3D integration. Multi-tier monolithic 3D integration stacks more than two silicon layers, thereby increasing the device density, which reduces the wire length and power consumption and improves performance further than two-tier monolithic 3D integration. Since the size of an MIV is comparable to that of a local via, the wire lengths of multi-tier gate-level monolithic 3D IC layouts are expected to be close to the ideal wire length reduction ratio, for example, 29, 42, and 50 percent for two-, three-, and four-tier designs, respectively. However, it is still unknown whether it would be possible to achieve the ideal wire length reduction ratios by multi-tier gate-level monolithic 3D integration. In this paper, we propose an efficient routing methodology to design multi-tier monolithic 3D ICs. Using the design methodology, we design two- to eight-tier gate-level monolithic 3D IC layouts and thoroughly investigate the wire length characteristics of the layouts. The simulation results show that the proposed routing methodology reduces the wire length by 12 to 53 percent compared to the 2D designs. In addition, the proposed routing methodology builds multi-tier monolithic 3D IC layouts more efficiently than a state-of-the-art methodology with comparable routed wire length.

In this paper, we present an optimization flow for monolithic 3D ICs called Pin-3D Optimizer. Compared with the state-of-the-art RTL-to-GDS flows that rely on ad-hoc technology file tweaks and RC scaling, Pin-3D offers a streamlined method to run commercial 2D IC tools to obtain high-quality monolithic 3D IC designs. Specifically, Pin-3D supports effective legalization, routing, timing closure, and ECO optimization for monolithic 3D IC designs. We propose a novel optimization methodology where the cells in each tier of a 3D IC are optimized using cell data and constraints of the full 3D design. The optimizations in a tier also directly influence the timing, power in the other tiers, leading to better overall PPA of the 3D IC. With the help of two industry processors designed with a 28 nm technology node, we show that Pin-3D provides up-to 9.0% smaller wirelength and 88% smaller total negative slack than die-by-die M3D flows. We also observe up-to 8.7% lower power and 26% smaller wirelength than 2D ICs. In addition, Pin-3D is the first flow that supports routing and timing optimization in heterogeneous logic-on-logic monolithic 3D ICs. We demonstrate this capability by performing area-balanced tier partitioning, routing, and timing closure of a 3D design with different technologies on each die.

Monolithic three-dimensional (3D) integration enables the most fine-grained integration of transistors by stacking very thin layers and fabricating monolithic inter-layer vias as small as local vias. Thus, monolithic 3D integration is expected to provide a higher degree of wirelength reduction, performance improvement, and power saving. Due to the prospective properties of the monolithic 3D integration technology, research on multilayer monolithic 3D integration that stacks more than two device layers is also ongoing. In this paper, we propose an algorithm that optimizes dynamic power consumption of gate-level monolithic 3D ICs. Under the same timing constraints, our algorithm reduces dynamic power consumption more effectively than a uniform-scaling-based placement algorithm. We also design multi-tier monolithic 3D ICs and show that our algorithm outperforms the uniform-scaling-based placement algorithm by 11.4% on average.

Monolithic 3D IC overcomes the limitation of the existing through-silicon-via (TSV) based 3D IC by providing denser vertical connections with nano-scale inter-layer vias (ILVs). In this paper, we demonstrate a thorough RTL-to-GDS design flow for monolithic 3D IC, which is based on commercial 2D place-and-route (P&R) tools and clever ways to extend them to handle 3D IC designs and simulations. We also provide a low-cost built-in-self-test (BIST) method to detect various faults that can occur on ILVs. Lastly, we present a resistive random access memory (ReRAM) compiler that generates memory modules that are to be integrated in monolithic 3D ICs.

Monolithic 3D ICs (M3D) are an emerging technology that offers an ultra-high-density 3D integration due to the extremely small size of monolithic inter-tier vias. We explore various design styles available in M3D and present design techniques to obtain GDSII-level signoff quality results for each of these styles. We also discuss various challenges facing each style and provide solutions to them.

As Moore's law approaches its physical limits, 3D integrated circuit (3D IC) technology has emerged as a crucial way to increase chip integration density. Due to their small size, high carrier mobility, and low power consumption, carbon nanotube field‐effect transistors (CNTFETs) offer a promising way to overcome the limitations imposed by Moore's law. The evolution of ICs and 3D integration technologies for the post‐Moore era, such as chiplets and multilayer stacking are reviewed, and the potential applications and value of CNTFETs in 3D optoelectronics, memory, and monolithic 3D ICs are explored. The prospects of novel device structures like FinFETs and gate‐all‐around FETs are also discussed. CNT 3D ICs have tremendous potential for these applications, but challenges remain in material fabrication, device performance, and 3D structure design. Researchers are actively exploring solutions such as optimizing fabrication processes, developing new materials, and innovative logic design methodologies. Notably, the integration of CNTFETs with chiplet technology promises more efficient and flexible chip design and manufacturing, catering to the future demand for high‐performance, low‐power, and high‐density ICs.

Monolithic 3D (M3D) ICs represent a significant advancement in VLSI technology, and unfortunately introduce a new dimension to the traditional, already NP-complete, 2D placement problem. A promising approach is to convert 2D placement into 3D placement using tier partitioning algorithms. Existing tier partitioning algorithms do not leverage historical data, such as prior placement configurations and performance metrics, that could improve efficiency and quality of placement. Utilizing historical data can help refine decision-making processes, reduce computational overhead, and enhance the overall effectiveness of tier partitioning strategies. To allow reuse of historical data, we propose a novel approach for M3D placement based on models and Reinforcement Learning (RL) that we name Dynamic Hierarchical Cluster Assignment with RL (DHCARL), which simplifies the search process by forming dynamic hierarchical clusters to preserve 2D placement when assigning clusters to 3D tiers. This approach uses a small set of parameters that enable effective reuse of historical data. With a Machine Learning (ML) model, low-code AutoML libraries help evaluate and select an RL policy. We propose novel Placement-aware graph networks (PAGN) to capture design connectivity and placement patterns in placement representation. We tested DHCARL on a diverse set of benchmarks, ranging from multiplexers (8- to 128-bit MuxShifter) to large-scale designs, including PicoRV32A, TATE-Pairing, and JPEG Encoder, implemented in 2-tiered and 4-tiered Monolithic 3D technology. Experimental results demonstrate that the proposed Reinforcement Learning-based Dynamic Hierarchical Assignment (DHCARL) approach outperforms state-of-the-art methods like TP-GNN and ART-3D, achieving a 6.3% lower placement cost on TATE-Pairing and 5.9% on PicoRV32A with similar runtime as TP-GNN.

The recent advancement of wafer bonding and monolithic integration technology offers fine-grained 3-D interconnections to face-to-face (F2F) and monolithic 3-D (M3D) ICs. In this article, we propose a full-chip RTL-to-GDSII physical design solution to build commercial-quality two-tier gate-level F2F and M3D ICs. The state-of-the-art flow named shrunk2D (S2D) requires shrinking of standard cells and interconnects by a factor of 50% to fit into the target 3-D footprint of a two-tier design. This, unfortunately, necessitates commercial place/route engines that handle one node smaller geometries, which can be challenging and costly. Our flow named compact-2D (C2D) does not require any geometry shrinking. Instead, C2D implements a 2-D IC with scaled interconnect RC parasitics and contracts the layout to the 3-D integrated circuit footprint. In addition, C2D offers post-tier-partitioning optimization (post-TP opt) which is completely missing in S2D. This additional optimization step is shown to be effective in fixing timing violations caused by inter-tier 3-D routing overhead. Lastly, we present a methodology to reuse the routing result of post-TP opt for the final GDSII generation. Our experimental results show that at iso-performance, C2D offers up to 28.0% power reduction and 15.6% silicon area savings over commercial 2-D ICs without any routing resource overhead.

Monolithic 3D ICs (M3D) are fabricated using a sequential process that grows new device and interconnect tiers in a bottom-up fashion. This fabrication process is in contrast to through-silicon via (TSV) technology that aligns and bonds pre-built tiers. M3D offers key advantages over TSVs, including (1) orders-of-magnitude smaller inter-tier vias, (2) no need for high alignment accuracy, (3) finer-grained tier partitioning options, etc. Recent studies have shown power, performance, area, and reliability (PPAR) advantages of M3D over TSV. However, M3D also suffers from its own problems, including (1) device and interconnect performance mismatch between tiers, (2) lack of EDA solutions, (3) testing challenges, (4) cost, etc. Research efforts have also been made to model and mitigate the impact of these undesirable characteristics of M3D. We will provide a survey of work that address the above issues and conclude with future directions.

Approaches to obtain monolithic 3D logic and memory ICs are proposed in this paper. 3–4x higher memory density with similar litho cost can be obtained with monolithic 3D memories, while benefits similar to a generation of scaling can be obtained with monolithic 3D logic by doubling the number of device layers. Well-known, manufacturing-friendly materials, process steps and device structures are used.

This study presents a novel approach for fabricating high-quality single-crystal germanium (Ge) films on insulators using a combination of silicon (Si) pillars, silicon nitride (SiNx) capping layers, and green nanosecond (GNS) pulsed laser crystallization. This method aims to advance monolithic three-dimensional integrated circuits (monolithic 3D ICs). Initially, the influence of the SiNx capping layer on the laser crystallization of Ge films is investigated. Based on these findings, the SiNx capping layer is integrated into the Ge on <tex>$\text{SiO}_{2}$</tex> with Si pillar structure, enabling the successful formation of single-crystal Ge films. The crystallinity of these films is validated through electron backscatter diffraction (EBSD), high-resolution transmission electron microscopy (HRTEM), and selected area electron diffraction (SAED), confirming their high-quality singlecrystalline nature. Additionally, thermal simulations indicate that the maximum substrate temperature remains below <tex>$400^{\circ} \mathrm{C}$</tex> during laser processing, ensuring compatibility with monolithic 3D ICs.

Operation characteristics of polycrystalline germanium (poly-Ge) tri-gate junctionless (JL) charge-trapping (CT) flash memory devices with bandgap-engineered tunneling layers fabricated by a low- temperature process were studied in this work. The poly-Ge tri-gate JL CT flash memory device with GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (GAS) stacked tunneling layer presents the highest programming speed and superior retention performance, due to the optimal bandgap-engineered in tunneling layer. Based on the simulation results, the GAS device has a higher tunneling current and more electrons can be captured in Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> to obtain larger V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shifts. The low-temperature fabrication process for poly-Ge CT flash memory device is promising for embedded memory in monolithic 3D IC.