Multi-Mode Segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and Test Time Reduction

The Network-on-Chip (NoC) is Network-version of System-on-Chip (SoC) means that on-chip communication through packet based networks. In NOC topology, routing algorithm and switching are main terminology. The routing algorithm is one of the key factors in NoC architecture. The routing algorithm which defines as the path taken by a packet between the source and the destination. The paper proposes a novel algorithm for a Network-on-Chip, which is based on packet switching. Using square mesh techniques used for 16 nodes based NoC design and simulation. The node is equal to row and column. Paper discusses internal architecture of NoC using addressable memory and simulate on XILINX 14.1 ISE MODELSIM. Keywords : Network-on-Chip, Static routing, Parallelism Cite this Article Anurag Shrivastava, Sudhir Kumar Sharma. A reliable routing architecture and algorithm for network-on-chip, Journal of Electronic Design and Technology . 2015; 6(3): 40–48p.

Broadcast-based test compression techniques can reduce both test data and test time. However, the success of such methods heavily depends on the percentage of test patterns that can be broadcasted. In this paper, we first conduct a quantitative analysis that shows the simple broadcast architecture that cannot achieve good test time/data compression even under a test set with very high level of don't care bits. A multi-mode-segmented scan test architecture (MSSA) is then presented to solve the problem of low broadcast rate. Three operation modes are supported in this architecture: broadcast, multicast and serial. As a result, improved test data compression is achievable with limited hardware overhead, as serial-mode operations are largely eliminated. An algorithm for the two-way partitions of the scan segments is proposed to construct multicast mode configurations. Finally, we present a layout-aware scan chain ordering method to further improve test compression. The problem of ordering scan cells in multiple scan chains is mapped to a constrained standard cell placement problem in physical synthesis, and the simulated annealing method is used to solve the problem. The routing length of the scan chains are also taken into account in the ordering process.

The increasing test data volume is considered as a biggest challenge in circuit under test. This challenge leads to higher computational complexity associated with the testing circuits. To reduce the testing time and addresses the problem related to high overhead, high fault coverage andincreased power dissipationmethod is used in system-on-chip (SoC). A new test compression method called divide and compress (D&C) lossless compression coder with Discrete Cosine Transformis used to enhance the compression capability. This framework of D&C lossless compression coder combines the lossless and lossy compression methods. The Discrete Cosine Transform (DCT) manipulates each data bit inside file and this reduces the file size without any data loss after decoding to lossless compression.Depending on the data characteristic, the compression of data is done without any loss in data. Further, the decompression is attained using advanced Finite State Machine (FSM) to reduce overhead. The experimental results on large benchmark circuits like ITC’99 and ISCAS’99 proves that the proposed D&C lossless compression attains reduced testing time and better compression ratio. Further, itlays only soft burden on the hardware.

Modern smart railroad management relies heavily on Internet of Things (IoT)-enabled sensors to monitor train performance, resulting in the generation of extensive data streams. The ensuing data influx poses critical challenges in storage, processing, and transmission. This paper presents a novel data compression method specifically designed for IoT-generated data within railroad management scenarios. Leveraging deep reinforcement learning (DRL), our approach intelligently compresses data from onboard IoT sensors. This not only streamlines data streams, ensuring essential information is retained and redundant data is pruned, but also alleviates strain on resource-limited devices such as edge servers tasked with complex computations or aggregating large datasets for long-term trend analysis. Experimental results demonstrate that our approach can outperform current baselines with achieving an enhancement of more than 18% on compression rate in real-time configurations. This signifies a transformative solution for handling IoT-induced big data in contemporary railroad management systems.

Integrated circuit (IC) applications have become viable, reliable, and cheaper with deep-submicron technologies in VLSI industry. SoC (system on chip) is a microchip, which holds the necessary hardware and software to implement various functions onto a single chip. An IC should be tested during design process to check the correctness of the design and also to check the functionality of the design after fabrication. Testing cost shares almost half of the manufacturing expenditure. Achieving high-test quality in reduced VLSI geometry increases the complexity of the testing methods because of huge volume of test data. Automatic testing equipment (ATE) reduces testing efforts, but it has limited memory in comparison with the huge volume of the test data. One of the methods to reduce the burden of ATE is test data compression. The advantages of test data compression are as follows: (i) reduction in memory requirement for ATE and (ii) reduction in testing time. Though many advanced algorithms are used for testing of VLSI circuits, most of them are expensive in terms of test data volume and power. This survey discusses all the test data compression methods, and it helps the researchers in testing domain.

Test data compression has been an effective way to reduce test data volume and test time, as well as to solve automatic test equipment (ATE) memory and bandwidth limitation. We analyze the limitations of current test data compression algorithm and draw on the previous experience to deduce an optimal compression coding model suitable for SoC test data. In addition, in this paper we make full use of the relevance of the test vectors and the advantages of statistical coding to present an efficient test data compression method RLE-G based on the coding model, and give the RLE-G the optimal compression efficiency of the boundary conditions and realization steps. The experimental results for ISCAS 89 benchmark circuits demonstrate RLE-G have the excellent advantages of high compression ratio.

During last decade, IEEE standard 1687 or IJTAG has been utilized to test the embedded instruments on chips that support test and measurement applications. Recently, IJTAG has been incorporated into the newly developed testing architecture referred as a Streaming Scan Network (SSN) for efficient testing of the complex System-on-Chips (SoCs). IJTAG registers are used to configure the components of a Streaming Scan Host (SSH) node associated with each core in the SSN network. SSN supports packetized test data distribution for streaming of the test data through SSN bus. SSN provides efficient SoC testing by several times reduction in test time and test data volume with limited pin count. Although SSN outshines in providing testing benefits, it lacks security support. An unauthorized user can maliciously modify the configuration registers and extracts sensitive information. Presence of untrusted modules in the network also amplifies the security concerns as each packet may contain test data of multiple cores. Hence, an untrusted cores can simply sniff the data destined for other cores. Therefore, to address the security issues in SSN test architecture, one needs to protect the system against internal untrusted third-party intellectual property (3PIP) modules and unauthorized users. This work discusses the security vulnerabilities of SSN architecture by demonstrating an attack scenario. Keeping the flexibility of SSN intact, we propose a modified SSH architecture and an authorization unit to ensure security against data sniffing attacks and unauthorized accesses, respectively. A state-of-the-art scheme is compared against the proposed approach in terms of area overheads. Thus, this paper presents a multi-level methodology with very low area and testing overheads for secure SSN.

This paper introduces a new IEEE standard, IEEE 802.15.5,which provides mesh capability for wireless personal area network (WPAN) devices. The standard provides an architectural framework enabling WPAN devices to promote interoperable, stable, and scalable wireless mesh topologies. It is composed of two parts: low-rate WPAN mesh and high-rate WPAN mesh. In this paper, we present only low-rate WPAN mesh because it is designed to support wireless sensor networks. IEEE 802.15.5 low-rate part is a light-weight scalable mesh routing protocol that caters well to the requirements of resource-constrained wireless sensor networks. By binding logical addresses to the network topology, IEEE 802.15.5 obviates the need for route discovery. This eliminates the initial route discovery latency, saves storage space and reduces the communication overhead and energy consumption. A distributed link state scheme is further built atop the block addressing scheme to improve the quality of routes, robustness, and load balancing. The routing scheme scales well with regard to various performance metrics. The standard also provides enhanced functions such as multicast, reliable broadcast, power saving, time synchronization, route tracing and portability. We also present the performance evaluation of major functions performed with a 50-nodes tested deployed over a whole floor (100 × 140 ft2) at CUNY Engineering building. The results testify that the IEEE 802.15.5 will serve well for wireless personal area networks and wireless sensor networks.

Increase in the speed of processors has led to crucial role of communication in the performance of systems. As a result, routing is taken into consideration as one of the most important subjects of the Network on Chip architecture. Routing algorithms to deadlock avoidance prevent packets route completely based on network traffic condition by means of restricting the route of packets. This action leads to less performance especially in non-uniform traffic patterns. On the other hand True Fully Adoptive Routing algorithm provides routing of packets completely based on traffic condition. However, deadlock detection and recovery mechanisms are needed to handle deadlocks. Use of global bus beside NoC as a parallel supportive environment, provide platform to offer advantages of both features of bus and NoC. This bus is useful for broadcast and multicast operations, sending delay sensitive signals, system management and other services. In this research, we use this bus as an escaping path for deadlock recovery technique. According to simulation results, this bus is suitable platform for deadlock recovery technique.

The differentiated services (DS) architecture provides a framework for the scalable provisioning of multiple service levels in the Internet. Its definition and initial work have concentrated mainly on per-hop behaviors (PHB) and mechanisms at each DS domain. Equally important is what happens between DS domains. Thanks to the flexibility of the architecture, it is the providers’ choice how to interconnect with peers. In principle, traditional, static peering agreements work together with DS, but they do not offer the flexibility and dynamics needed in an electronic market for network capacity. Therefore, we look at dynamic service level agreements at the interdomain level. Such agreements are established by software entities called traders. These traders follow market-based principles to decide which contracts will be beneficial. In particular, traders compare the offers made by neighbor providers and select the most interesting ones. This selection of peer services creates competition among providers and integrates route selection based on service level and destination. We describe and implement a framework for service level agreement trading. We show the basic workings and first performance results of SLA trading using specific traders and an experimentally defined PHB in a simulation environment. Keywords— Network architecture, differentiated services architecture, service level agreement, pricing, trading, interdomain QoS routing.

Wireless body area network (WBAN) is an emerging technology which is getting a lot of attention these days due to its application in medical field and health monitoring system. In this technology by using different bio-sensors which could be implanted or worn by patient, he/she get his/her health conditions at regular intervals. Wireless connectivity makes it more popular because of its patient could use it in his daily life activities also. There are various fields in WBAN where a lot of development could be made, as this field is still in its developing stages. Efficient energy utilisation techniques have been explained. Routing metrices which consists of residual energy, delay, packet collision, network lifetime, complexity, network traffic etc. is also an interesting area where we will be working to develop intelligent routing metrices for wireless body Area Network (WBAN).Fuzzy Logic(FL) is a powerful tool used to develop solution of various problems today which maps the crisps inputs to give corresponding outputs. Momdani Fuzzy Inference System (FIS) provides the atmosphere needed for Fuzzy Logics where depending on degree of membership functions maps the variables and a surface is generated with respect to various factors in routing metrics. In this paper we had reviewed its basic aspects like its constituents, layered architecture and Issues as well as requirements of WBAN with Fuzzy Inference System (FIS). Keywords: Wireless Body Area Network, WBAN, Routing Metrices, Layered Architecture, Fuzzy Logic, Energy efficiency, Fuzzy Inference System (FIS).

In this thesis, concepts for developing Spatial Data Infrastructures with an emphasis on visualizing 3D landscape and city models in distributed environments are discussed. Spatial Data Infrastructures are important for public authorities in order to perform tasks on a daily basis, and serve as research topic in geo-informatics. Joint initiatives at national and international level exist for harmonizing procedures and technologies. Interoperability is an important aspect in this context - as enabling technology for sharing, distributing, and connecting geospatial data and services. The Open Geospatial Consortium is the main driver for developing international standards in this sector and includes government agencies, universities and private companies in a consensus process. 
\n3D city models are becoming increasingly popular not only in desktop Virtual Reality applications but also for being used in professional purposes by public authorities. Spatial Data Infrastructures focus so far on the storage and exchange of 3D building and elevation data. For efficient streaming and visualization of spatial 3D data in distributed network environments such as the internet, concepts from the area of real time 3D Computer Graphics must be applied and combined with Geographic Information Systems (GIS). For example, scene graph data structures are commonly used for creating complex and dynamic 3D environments for computer games and Virtual Reality applications, but have not been introduced in GIS so far. 
\nIn this thesis, several aspects of how to create interoperable and service-based environments for 3D spatial data are addressed. These aspects are covered by publications in journals and conference proceedings. The introductory chapter provides a logic succession from geometrical operations for processing raw data, to data integration patterns, to system designs of single components, to service interface descriptions and workflows, and finally to an architecture of a complete distributed service network.
\nDigital Elevation Models are very important in 3D geo-visualization systems. Data structures, methods and processes are described for making them available in service based infrastructures. A specific mesh reduction method is used for generating lower levels of detail from very large point data sets. An integration technique is presented that allows the combination with 2D GIS data such as roads and land use areas. This approach allows using another optimization technique that greatly improves the usability for immersive 3D applications such as pedestrian navigation: flattening road and water surfaces. It is a geometric operation, which uses data structures and algorithms found in numerical simulation software implementing Finite Element Methods. 
\n3D Routing is presented as a typical application scenario for detailed 3D city models. Specific problems such as bridges, overpasses and multilevel networks are addressed and possible solutions described. The integration of routing capabilities in service infrastructures can be accomplished with standards of the Open Geospatial Consortium. An additional service is described for creating 3D networks and for generating 3D routes on the fly. Visualization of indoor routes requires different representation techniques.
\nAs server interface for providing access to all 3D data, the Web 3D Service has been used and further developed. Integrating and handling scene graph data is described in order to create rich virtual environments. Coordinate transformations of scene graphs are described in detail, which is an important aspect for ensuring interoperability between systems using different spatial reference systems. The Web 3D Service plays a central part in nearly all experiments that have been carried out. It does not only provide the means for interactive web-visualizations, but also for performing further analyses, accessing detailed feature information, and for automatic content discovery.
\nOpenStreetMap and other worldwide available datasets are used for developing a complete architecture demonstrating the scalability of 3D Spatial Data Infrastructures. Its suitability for creating 3D city models is analyzed, according to requirements set by international standards. A full virtual globe system has been developed based on OpenStreetMap including data processing, database storage, web streaming and a visualization client.
\nResults are discussed and compared to similar approaches within geo-informatics research, clarifying in which application scenarios and under which requirements the approaches in this thesis can be applied.
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A new segmented architecture is presented to improve the dynamic and static performance of the current steering digital-to-analog converters (DACs). In the proposed architecture instead of a single...

Mobile ad hoc network (MANET) is kind of wireless networks architecture, which is an infrastructureless, autonomous, stand-alone network. Therefore, MANET can be flexibly and simply deployed in almost any environment. But it has a limited wireless coverage and limited connectivity that is exclusive to the MANET boundary. The growth of the Internet and its services and applications and the trend in fourth generation (4G) wireless networks toward full-IP networks, lead to an increasing demand for enabling MANET nodes to connect to Internet and use its services and applications. Mobile IP and IP micro-mobility protocols enable the mobile host to access Internet and change points of attachment without losing the connection. So, with the cooperation between MANET routing protocols and IP mobility protocol, Internet connectivity to MANET nodes can be achieved. In this paper, we propose integrated network architecture to extend the cellular IP access network to multiple MANETs. We also propose an integration routing protocol for connecting MANET to cellular IP Access network and Internet. The proposed protocol supports mobile nodes mobility between different MANETs.

Telecom operators' proliferation, caused by the liberation in the provision of communication services in the European domain, has led in the emergence of demand for small, cost effective core network elements capable of performing both access communication, as well as, traffic routing towards various technology backbones. Bulky equipment is no longer attracting operators' interest, for a number of reasons, summarized in downsize ability (monolithic support of millions of users on a single box is not the case anymore for start up operators), scalability and flexibility to seamlessly integrate advanced services. Especially in the case of UMTS, IP communications are realized over a mixture of heterogeneous transportation technologies often resulting to replication of redundant functions, which limits network performance, complicates its maintenance, reduces scalability and increases operational costs. This paper presents a flexible gateway architecture, which can be accommodated on the access interfaces of UMTS networks to enable realization of generic communication interfaces towards core network databases, supporting user access and traffic routing functions, for improved IP communications performance, enhances UMTS network scalability and reduces maintenance costs. Architectural modularity is achieved by integrating the various database technologies within a common network architecture utilising Storage Area Networks technology.