Multi-spectral snapshot diffraction-based overlay metrology.

Overlay (OVL) is one significant performance indicator for the lithography process control in semiconductor manufacturing. The accuracy of the OVL metrology is extremely critical for guarantee the lithography quality. Currently, diffraction-based overlay (DBO) is one of the mainstream OVL metrology techniques. Unfortunately, the accuracy of the DBO metrology is largely affected by the defect features of the OVL target. Therefore, there is a strong need to investigate the impacts of these target defects on the DBO metrology performance. However, efficiently investigating the statistical and interactive impacts of various DBO target defects remains challenging. This study aims to address this issue through proposing an intelligent sensitivity analysis approach. A cumulative distribution based global sensitivity analysis (GSA) method is utilized to assess the nonlinear influences of multiple defects in the OVL target on the DBO inaccuracy. The scenarios with both known and unknown distributions of the OVL target defects are considered. For the former, a neural network driven forward model is constructed for fast calculating the optical diffraction responses to accelerate the GSA process. For the latter, another neural network based inverse model are built for efficiently estimating the distribution of the target defects. Finally, a series of simulation experiments are conduct for typical DBO targets with multiple common defect features. The results demonstrate the effectiveness and robustness of the proposed approach as well as give valuable insights into the DBO defect analysis. Our study provides a strong tool to assist the practitioners in achieving intelligent and efficient DBO analysis and thus in enhancing OVL metrology performance.

Overlay error in lithography refers to the positional deviation between the patterns of two exposures and is one of the key indicators for evaluating lithography quality. Traditional overlay metrology methods are limited by the intensity of higher-order diffraction energy and mostly rely on ±1st-order diffraction light for measurements, making them susceptible to variations in the mark structure. This project proposes a diffraction-order-enhanced overlay error metrology method utilizing multiple diffraction orders. First, the scalar diffraction theory is used to derive the method for enhancing grating diffraction efficiency and explain the advantages of higher diffraction orders. Then, the Rigorous Coupled-Wave Analysis (RCWA) algorithm is used to simulate the optimized overlay (OVL) mark, demonstrating the effectiveness of the design. This method can compensate for the issue of certain wavelengths being difficult to use due to large measurement errors, achieving sub-nanometer precision while reducing sensitivity to polarization direction. By using the method of shared multiple diffraction orders, it is possible to corrected situations that are unavailable when only using ±1st order, providing more recipe options for multi-wavelength Diffraction-Based Overlay (DBO) technology. Our study presents an ingenious approach to mark optimization, enabling practitioners to make more flexible choices when dealing with different product batches, thereby enhancing the accuracy and robustness of OVL measurement.

Optical overlay metrology has been adopted for years as baseline for overlay control in semiconductor manufacturing. More stringent overlay budget for securing good product yield has been required as device dimension shrinkage. For effective and tight overlay control, the traditional optical overlay metrology has faced two primary challenges of increasing the measurement accuracy and minimizing the measurement variance between overlay mark in scribe lane and in-die device pattern. Overlay mark asymmetry is one of the general factors to induce optical overlay metrology error. While 3D-NAND deep-etch processes would induce within-wafer mark asymmetry which worsens measurement robustness of optical overlay metrology. Accurately determining on-product overlay (OPO) errors at both after-develop inspection (ADI) and after-etch inspection (AEI) is also desirable in 3D-NAND process for applying non-zero offset (NZO) at photo exposure. To address the measurement robustness of optical overlay metrology in 3D-NAND process, also for accurately bridging the scribe lane based optical overlay metrology to OPO metrology, a complementary overlay metrology by high voltage scanning electron microscope (HV-SEM) was adopted as the reference metrology for optimizing the optical measurement condition on scribe lane targets. In this paper, the measurement accuracy of imaging-based overlay (IBO) target under various optical conditions was calibrated by HV-SEM. HV-SEM can measure both the scribe-lane and in-device targets via capturing buried structures, and it was employed to bridge the measurement results from IBO and in-device target. Then the optimal optical metrology can be decided for both ADI and AEI to facilitate effective advance process control (APC) and NZO purpose.

With the increase of process complexity in advanced nodes, the requirements of process robustness in overlay metrology continues to tighten. Especially with the introduction of newer materials in the film-stack along with typical stack variations (thickness, optical properties, profile asymmetry etc.), the signal formation physics in diffraction-based overlay (DBO) becomes an important aspect to apply in overlay metrology target and recipe selection. In order to address the signal formation physics, an effort is made towards studying the swing-curve phenomena through wavelength and polarizations on production stacks using simulations as well as experimental technique using DBO. The results provide a wealth of information on target and recipe selection for robustness. Details from simulation and measurements will be reported in this technical publication.

The use of optical metrology techniques in process control for microelectronic manufacturing has become widespread. These techniques are fast and non-destructive, allowing a higher sampling rate than non-optical methods like scanning electron or atomic force microscopy. One drawback of most optical metrology tools is the requirement that special measurement structures be fabricated in the scribe line between chips. This poses significant limitations regarding the characterization of lithography processes that may be overcome via in-chip measurements. In this paper we present experimental results for an in-chip optical metrology technique that allows direct measurement of both critical dimensions and overlay displacement errors in the DRAM manufacturing process. This technique does not require special target structures and is performed on the actual semiconductor devices.

In leading edge patterning processes, overlay is now entangled with CD including OPC residuals and stochastics. This combined effect is a serious challenge for continued shrink and can be characterized with an Edge Placement Error (EPE) budget containing multi-domain components: global and local CD, local placement errors, overlay errors, etch biases and OPC. EPE defines process capability and ultimately relates to device yield. Understanding the EPE budget leads to efficient ways to monitor process capability and optimize it using EPE based process control applications. We examine a critical EPE use case on a leading edge DRAM node. We start by constructing and verifying the EPE Budget via densely sampled on-product in-device local, global CD and Overlay metrology after the etch process step. EPE budget contributors are ranked according to their impact to overall EPE performance and later with simulated EPE performance improvements per component. A cost/benefit analysis is shown to help choose the most HVM-friendly solutions.

Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. While uniform process-induced stress is easily corrected, non-uniform stress across the wafer is much more problematic, often resulting in non-correctable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such non-uniform stress. We will describe a Patterned Wafer Geometry (PWG) tool, which uses optical methods to measure the geometry of in-process wafers. PWG data can be related to In-Plane Distortion (IPD) of the wafer through the PIR (Predicted IPD Residual) metric. This paper will explore the relationship between the PIR data and measured overlay data on Engineered Stress Monitor (ESM) wafers containing various designed stress variations. The process used to fabricate ESM wafers is quite versatile and can mimic many different stress variation signatures. For this study, ESM wafers were built with strong across-wafer stress variation and another ESM wafer set was built with strong intrafield stress variation. IPD was extensively characterized in two different ways: using standard overlay error metrology and using PWG metrology. Strong correlation is observed between these two independent sets of data, indicating that the PIR metric is able to clearly see wafer distortions. We have taken another step forward by using PIR data from the PWG tool to correct process-induced overlay error by feedforward to the exposure tool, a novel method that we call PWG-FF. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.

As semiconductor end markets diversified from computers and Internet to mobile and social media, computing demand increased from hundreds of millions to billions of units. With the advent of AI, and big data end markets further diversified to IOT, communications, self-driving cars, power, and sensors, resulting in demand for computing that ski-rocketed to the trillions. To fuel this growth PPACt :Power, Performance, Area-cost and time-to-market needed to accelerate. This acceleration is enabled by new architectures, 3D structures, new materials, new ways to shrink, and advanced packaging. An obstacle limiting this growth was identified as loss of correlation between the new aforementioned semiconductor device structures, and the measurements conventional optical workhorse metrology provided. This was not a one-time calibration event. Optical metrology increased reliance on accuracy check, ground truth and calibration is a result of increasing optical metrology accuracy gaps over time, causing inflating edge placement error budgets, instability in litho to etch bias and non-zero offset over time. A paradigm shift in overlay, CDU, and edge placement error patterning control metrology was sought to accelerate PPACt at needed yield. This talk tells the story of how to introduce a new standard to a needing industry. We start with addressing the need for a new technology enabling a fast non-destructive accurate inline metrology, we then validate its accuracy overtime using two different industry standard reference metrologies. And we conclude with testimonies of chipmakers showcasing the use of the new industry standard of patterning control. To enable high throughput accuracy in overlay, EPE, and NZO metrology a highly efficient BSE see-through ebeam technology was introduced and benchmarked against optical metrology. Showing reduced non zero offset residuals on device, with the capability to accurately gauge litho-to-etch bias. As a good engineering practice STEM and Delayer techniques validated the accuracy of the inline ebeam technology so it could become the new workhorse to assume the role of HVM overlay metrology. We conclude with three chipmakers case studies of how the use of the new workhorse ebeam metrology accelerated cycles of development, reduced reliance on destructive metrology enabling faster process splits in fabrication of three dimensional nanosheet transistors, faster ramp of semiconductor manufacturing and better yield by better on device overlay and NZO at HVM.

As the design rule of semiconductor devices shrinks to below 100nm dimensions, the degree of pattern alignment from different process levels has become a crucial factor affecting both process control and induced defect on unit process. Isolated and dense patterns were formed at process layers from front-end through to back-end on wafers using sub 100nm device process utilizing ArF lithography under various lithography conditions. As pattern size is reduced, overlay discrepancies become larger. The OL (overlay) error is very important because the pattern misalignment induces critical defects for the device. For many years, overlay metrology for process control has been measured by 4-corner box-in-box methods in chip. OL errors and CD (Critical Dimension) values have been measured on different tool. CD values have been measured on SEMs (Scanning Electron Microscope) and OL errors have been measured on optical tools. The accuracy of OL error metrology is limited by the resolution of tool, which is on the order of 1μm. In this paper we calculated the degree of overlay errors (current level to prior level errors) through a process patterns images obtained from a CD-SEM.

We have developed a new local overlay measurement technique on actual device patterns using a critical dimension scanning electron microscope (CD-SEM), which can be applied to two-dimensional (2D) device structures such as a static random access memory contact hole array. CD-SEM overlay measurement can provide additional local overlay information at the site of device patterns, complementary to the optical overlay. The methodology includes the use of pattern symmetry to cancel out many process effects and reduce measurement uncertainty. CD-SEM overlay metrology was compared with conventional optical overlay metrology in terms of measurement uncertainty and overlay model analysis, and very good correlation was confirmed. The developed methodology was applied to local overlay measurement of double patterning contact hole layers of leading edge devices. The local overlay distribution was obtained across the device area, and spatial correlation of the overlay error vectors was examined over a large range of distances. The applications of CD-SEM overlay metrology were explored, and methodologies were introduced to examine both the overlay of double patterning contacts at the edge of an array and lithographic process-induced overlay shift of contacts. Finally, a hybrid optical CD-SEM overlay metrology was introduced in order to capture a high order, device weighted overlay response.

The center for measurement standards (CMS) has a research program in optical overlay metrology. The main goal of this work is to improve overlay measurement accuracy. Two main threads are developed to the work - novel in-chip overlay target design, and best algorithm. The former is hoped to prove a capability for measuring overlay error inside the active area of product devices. The later is for extracting the most from image detail.

Metal containing resists (MCR) are one of the candidates for Extreme Ultraviolet (EUV) resists aiming to achieve the resolution, linewidth roughness and sensitivity (RLS) requirements of advanced design nodes. MCRs intrinsically have high etch resistance owing to their metal content. Therefore, low resist thickness (~18nm) is sufficient to transfer resist patterns into an underlying hard mask. Also, the thin resist reduces susceptibility to pattern collapse during development because of low aspect ratio. However, thus far little attention has been paid to optical metrology and inspectability (overlay, defect inspection, scatterometry, etc.) of these resists, which is another critical requirement to move MCR toward high volume manufacturing (HVM). In this paper, we investigate overlay metrology and overlay correction with MCR. Even though the optical contrast for MCR is slightly lower than for chemically amplified resist (CAR) it seemed sufficient for high-quality overlay metrology. However, the measurement precision for MCR is deteriorated compared to that for CAR, resulting in significantly higher residuals. The root cause of the deteriorated measurement precision was found in grains in the optical image after MCR development. Interestingly, the after etch performance of CAR and MCR is identical. We demonstrate that with sufficient sampling, appropriate correctables can be extracted from the MCR overlay results. Finally, we discuss how the increased image noise can be compensated by the applied sampling scheme.

The objective of this work is to determine a guideline for defining practical overlay metrology requirements for a given design rule. Total measurement uncertainty (TMU) of overlay metrology is defined as the square root of square sum of the following items: the mean of the tool-induced shift (TIS), TIS 3-sigma, dynamic precision, and tool-to-tool matching. The TMU is dependent upon process conditions, so TMU is different by process layer. In this study, the impact of TMU on overlay error correction, which includes process and measurement noise, is investigated in terms of the stability of high-order overlay correction parameters. By evaluating the variation range of correctable parameters as a figure of merit, the corresponding TMU is determined for a given design rule. Utilizing this methodology, we determined that 2 nm of TMU value is the allowable limit for 45 nm of dynamic random access memory (DRAM) half pitch based upon simulation results. Similarly, we recommend 1 nm of TMU for 36 nm of DRAM half pitch. Our methodology is described and our simulation results are discussed.

Optical lithography, currently being used for 45-nm semiconductor devices, is expected to be extended further towards the 32-nm and 22-nm node. A further increase of lens NA will not be possible but fortunately the shrink can be enabled with new resolution enhancement methods like source mask optimization (SMO) and double patterning techniques (DPT). These new applications lower the k1 dramatically and require very tight overlay control and CD control to be successful. In addition, overall cost per wafer needs to be lowered to make the production of semiconductor devices acceptable. For this ultimate era of optical lithography we have developed the next generation dual stage NXT:1950i immersion platform. This system delivers wafer throughput of 175 wafers per hour together with an overlay of 2.5nm. Several extensions are offered enabling 200 wafers per hour and improved imaging and on product overlay. The high productivity is achieved using a dual wafer stage with planar motor that enables a high acceleration and high scan speed. With the dual stage concept wafer metrology is performed in parallel with the wafer exposure. The free moving planar stage has reduced overhead during chuck exchange which also improves litho tool productivity. In general, overlay contributors are coming from the lithography system, the mask and the processing. Main contributors for the scanner system are thermal wafer and stage control, lens aberration control, stage positioning and alignment. The back-bone of the NXT:1950i enhanced overlay performance is the novel short beam fixed length encoder grid-plate positioning system. By eliminating the variable length interferometer system used in the previous generation scanners the sensitivity to thermal and flow disturbances are largely reduced. The alignment accuracy and the alignment sensitivity for process layers are improved with the SMASH alignment sensor. A high number of alignment marker pairs can be used without throughput loss, and furthermore the GridMapper functionality which is using the inter-die and intra-die scanner capability can reduce overlay errors coming from mask and process without productivity impact. In this paper we will present the main design features and discuss the system performance of the NXT:1950i system, focusing on the improvements made in overlay and productivity. We will show data on imaging, overlay, focus and productivity supporting the 3X-nm node and we will discuss next improvement steps towards the 2X-nm node.

Rapid tuning of a dye laser over a large wavelength range has been achieved by inserting an acoustooptic deflector between the dye cell and a diffraction grating. The deflector and grating combination serve as the tuning element. TeO(2), which has an anomalously low sound velocity, has been used to demonstrate acoustooptical tuning over a broad spectral range. Theoretically, tuning rates greater than 100 nm/microsec can be achieved over a wavelength range of up to 35 nm. The experimental data have been used to verify the analytical aspects of the beam deflector and diffraction grating configuration.