Multiparty Equality Function Computation in Networks with Point-to-Point Links

The problem of how to efficiently maintain a large number (say millions) of statistics counters that need to be incremented at very high speed has received considerable research attention recently. This problem arises in a variety of router management algorithms and data streaming algorithms, where a large array of counters is used to track various network statistics and to implement various counting sketches respectively. While fitting these counters entirely in SRAM meets the access speed requirement, a large amount of SRAM may be needed with a typical counter size of 32 or 64 bits, and hence the high cost. Solutions proposed in recent works have used hybrid architectures where small counters in SRAM are incremented at high speed, and occasionally written back ("flushed") to larger counters in DRAM. Previous solutions have used complex schedulers with tree-like or heap data structures to pick which counters in SRAM are about to overflow, and flush them to the corresponding DRAM counters.In this work, we present a novel hybrid SRAM/DRAM counter architecture that consumes much less SRAM and has a much simpler design of the scheduler than previous approaches. We show, in fact, that our design is optimal in the sense that for a given speed difference between SRAM and DRAM, our design uses the theoretically minimum number of bits per counter in SRAM. Our design uses a small write-back buffer (in SRAM) that stores indices of the overflowed counters (to be flushed to DRAM) and an extremely simple randomized algorithm to statistically guarantee that SRAM counters do not overflow in bursts large enough to fill up the write-back buffer even in the worst case. The statistical guarantee of the algorithm is proven using a combination of worst case analysis for characterizing the worst case counter increment sequence and a new tail bound theorem for bounding the probability of filling up the write-back buffer. Experiments with real Internet traffic traces show that the buffer size required in practice is significantly smaller than needed in the worst case.

Tree exploration with advice

We study the amount of knowledge about the network that is required in order to efficiently solve a task concerning this network. The impact of available information on the efficiency of solving network problems, such as communication or exploration, has been investigated before but assumptions concerned availability of particular items of information about the network, such as the size, the diameter, or a map of the network. In contrast, our approach is quantitative: we investigate the minimum number of bits of information (minimum oracle size) that has to be given to an algorithm in order to perform a task with given efficiency. We illustrate this quantitative approach to available knowledge by the task of tree exploration. A mobile entity (robot) has to traverse all edges of an unknown tree, using as few edge traversals as possible. The quality of an exploration algorithm ${\cal A}$ is measured by its competitive ratio, i.e., by comparing its cost (number of edge traversals) to the length of the shortest path containing all edges of the tree. Depth-First-Search has competitive ratio 2 and, in the absence of any information about the tree, no algorithm can beat this value. We determine the minimum number of bits of information that has to be given to an exploration algorithm in order to achieve competitive ratio strictly smaller than 2. Our main result establishes an exact threshold oracle size that turns out to be roughly loglogD, where D is the diameter of the tree. More precisely, for any constant c, we construct an exploration algorithm with competitive ratio smaller than 2, using an oracle of size at most loglogD –c, and we show that every algorithm using an oracle of size loglogD –g(D), for any function g unbounded from above, has competitive ratio at least 2.

The potential gains of multiple antennas in wireless systems can be limited by channel state information imperfections. In this context, this paper tackles the limited feedback in multiuser correlated multiple input single output (MU-MISO). We propose a framework to feedback the minimum number of bits with limited performance degradation. This framework is based on decor relating the channel state information by compression and then quantize the compressed (CSI) and feedback it to the base station (BS). We characterize the rate loIEEss resulting from the proposed framework. An upper bound on the rate loss is derived in terms of the amount of feedback and the statistics of the channel. Based on this characterization, we propose an adaptive bit allocation algorithm that takes into the account the channel statistics to reduce the rate loss induced by the quantization. Moreover, in order to maintain a constant rate loss with respect to perfect CSI, it is shown that the number of feedback bits should scale linearly with the SNR (in dB) and to the rank of the user transmit correlation matrix. We validate the proposed framework by Monte-carlo simulations.

A simulation of an interactive protocol entails the use of interactive communication to produce the output of the protocol to within a fixed statistical distance e. Recent works have proposed that the information complexity of the protocol plays a central role in characterizing the minimum number of bits that the parties must exchange for a successful simulation, namely the distributional communication complexity of simulating the protocol. Several simulation protocols have been proposed with communication complexity depending on the information complexity of the simulated protocol. However, in the absence of any general lower bounds for distributional communication complexity, the conjectured central role of information complexity is far from settled. We fill this gap and show that the distributional communication complexity of e-simulating a protocol is bounded below by the e-tail λe of the information complexity density, a random variable with information complexity as its expected value. For protocols with bounded number of rounds, we give a simulation protocol that yields a matching upper bound. Thus, it is not information complexity but λe that governs the distributional communication complexity.As applications of our bounds, in the amortized regime for product protocols, we identify the exact second order term, together with the precise dependence on e. For general protocols such as a mixture of two product protocols or for the amortized case when the repetitions are not independent, we derive a general formula for the leading asymptotic term. These results sharpen and significantly extend known results in the amortized regime. In the single-shot regime, our lower bound sheds light on the dependence of communication complexity on e. We illustrate this with an example that exhibits an arbitrary separation between distributional communication complexity and information complexity for all sufficiently small $\ep$.

Fast radio broadcasting with advice

The implementation of data acquisition and real-time backprojection via a bit-slice microprocessor system places serious constraints on data format in TOF-PET systems. To minimize hardware costs and complexity and enhance processing speed, internal data representation is to be realized with a minimum number of bits without significant loss of accuracy. Specifically, we have examined in detail data formats necessary for the quantization of the TOF data and reconstruction filtering via integer FFT's. Estimates of data degradation as related to number of bits utilized have been obtained. It is shown that a significant reduction in image memory size and improvement in speed of computation can be achieved with the appropriate choice of data formats and algorithms.

In this paper we show an information-theoretic lower bound of kn - o(kn) on the minimum number of bits to represent an unlabeled simple connected n-node graph of pagenumber k. This has to be compared with the efficient encoding scheme of Munro and Raman of 2kn + 2m + o(kn+m) bits (m the number of edges), that is 4kn + 2n + o(kn) bits in the worst-case. For m-edge graphs of pagenumber k (with multi-edges and loops), we propose a 2mlog2k + O(m) bits encoding improving the best previous upper bound of Munro and Raman whenever m ≤ 1 / 2kn/log2 k. Actually our scheme applies to k-page embedding containing multi-edge and loops. Moreover, with an auxiliary table of o(m log k) bits, our coding supports (1) the computation of the degree of a node in constant time, (2) adjacency queries with O(logk) queries of type rank, select and match, that is in O(logk *minlogk / loglogm, loglogk) time and (3) the access to δ neighbors in O(δ) runs of select, rank or match;.

This paper describes a field-programmable gate array (FPGA) implementation of a fixed-point low-density lattice code (LDLC) decoder where the Gaussian mixture messages that are exchanged during the iterative decoding process are approximated to a single Gaussian. A detailed quantization study is first performed to find the minimum number of bits required for the fixed-point decoder to attain a frame error rate (FER) performance similar to floating-point. Then efficient numerical methods are devised to approximate the required non-linear functions. Finally, the paper presents a comparison of the performance of the different decoder architectures as well as a detailed analysis of the resource requirements and throughput trade-offs of the primary design blocks for the different architectures. A novel pipelined LDLC decoder architecture is proposed where resource re-utilization along with pipelining allows for a parallelism equivalent to 50 variable nodes on the target FPGA device. The pipelined architecture attains a throughput of 10.5 Msymbols/sec at a distance of 5 dB from capacity which is a 1.8times improvement in throughput compared to an implementation with 20 parallel variable nodes without pipelining. This implementation also achieves 24times improvement in throughput over a baseline serial decoder.

Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computations and meet time-to-market pressures. We present a compiler that takes as input algorithms described in MATLAB and generates RTL VHDL. The RTL VHDL then can be mapped to FPGAs using existing commercial tools. The input application is mapped to multiple FPGAs by parallelizing the application and embedding communication and synchronization primitives automatically. Our compiler infers the minimum number of bits required to represent the variable through a precision analysis framework. The compiler can leverage optimized IP cores to enhance the hardware generated. The compiler also exploits parallelism in the input algorithm by pipelining in the presence of resource constraints. We demonstrate the utility of the compiler by synthesizing hardware for a couple of signal/image processing algorithms and comparing them with manually designed hardware.

In the last decade we have witnessed substantial progress towards the application of vocoders in communications and multimedia. Vocoders are typically based on a source‐system model whose parameters are encoded in a compact binary format. The objective in voice or speech coding is to represent speech with a minimum number of bits while preserving its perceptual quality. A number of vocoders are embedded in cellular and multimedia standards. The objective of this chapter is to provide a review of vocoding algorithms with emphasis on those methods that are part of telephony standards

In this paper an algorithm to generate an optimum initial state assignment for Finite State Machines is presented, that in combination with the Kantabutra-Andreou method (1994) can provide a state assignment with the minimum number of bits.

The scheme proposed in this paper balances the partly conflicting objectives of meeting the diverse quality of service (QoS) needs of mobile hosts (MHs) and achieving high uplink throughput in a Direct Sequence Code Division Multiple Access (DS-CDMA) based cellular network. The QoS needs of the MHs are modeled using the notion of a service curve, which is a function characterizing the minimum number of bits a MH must transmit in any given time interval in order to meet its QoS requirement. Each MH is also assumed to have a specified bound on the acceptable bit error rate.The technique proposed in this paper maximizes the uplink throughput subject to the service curve constraints by jointly adapting the transmitted power and the number of spreading codes used by each MH in relaying its data bits. During this joint adaptation, the technique also imposes specified bounds on the transmitted power and the number of spreading codes that a MH can handle. The proposed technique is evaluated using a discrete-event simulation. The evaluation shows that the proposed scheme can effectively balance the two above-mentioned objectives.

Let M = {0, 1, 2, ..., m—1} , N = {0, 1, 2,..., n—1} , and f:M × N → {0, 1} a Boolean-valued function. We will be interested in the following problem and its related questions. Let i e M, j e N be integers known only to two persons P1 and P2, respectively. For P1 and P2 to determine cooperatively the value f(i, j), they send information to each other alternately, one bit at a time, according to some algorithm. The quantity of interest, which measures the information exchange necessary for computing f, is the minimum number of bits exchanged in any algorithm. For example, if f(i, j) = (i + j) mod 2. then 1 bit of information (conveying whether i is odd) sent from P1 to P2 will enable P2 to determine f(i, j), and this is clearly the best possible. The above problem is a variation of a model of Abelson [1] concerning information transfer in distributive computions.

The aim of our work is to realize the implementation of a real-time high-quality image rotation on FPGA's board. The method we used is based on M. Unser's work and consists in applying a B-spline interpolator. The difficulty of this problem is due to the relatively weak integration capacity of FPGAs. To solve this problem we have searched for determining the minimum number of bits to code the filter while keeping a good accuracy of filtering output. In this article, we remind a few definitions about B-spline functions and we present how we use B- spline interpolation for the image rotation problem. Then, we describe the way we calculate probability density function of the output error in order to determine the filter data coding.