Multiple Fault Detection in Programmable Logic Arrays

It is relatively easy to generate a complete single contact fault detection test set Tc for a PLA. However such a test set may fail to detect all multiple faults due to the phenomenon of masking. In previous papers attempting to quantitatively predict the multiple fault coverage capability of a single fault detection test set Tc in PLA's, it was proved that every multiple contact fault in an irredundant PLA is detected by Tc if the multiple fault does not contain any four-way masking cycle. In this correspondence, the masking relations are studied in detail and it is shown that Tc in fact detects a signifilcant percentage of faults with four-way masking. Based on these results more realistic bounds of the coverage capability of Tc are determined. It is shown that the multiple fault coverage ratio of Tc increases with the increasing number m of rows of a PLA and for m = 24 Tc detects 99 percent of all contact faults of size 8 or less.

This paper presents a practical and low cost design-for-testability (DFT) scheme for the row-based field programmable gate array (FPGA) which is widely used for rapid prototyping, hardware verification/emulation of VLSI chips and manufacturing of complex digital systems. A new module is introduced for the DFT of the FPGA. The proposed DFT scheme permits the uncommitted FPGA to be tested using a set of constant cardinality (C-testability) for single and multiple stuck-at fault detection, while reducing the number of required primary test pins to only one. The number of tests for the FPGA is still 8+n/sub f/ (where n/sub f/ is the number of sequential modules in a row of the array), but only one primary pin and a small amount of testing circuitry are now required. This paper also modifies the single fault test set to accomplish multiple fault detection under two multiple fault models: the multiple fault single module (MFSM) and the single fault multiple module (SFMM) models. It is shown that by appropriately changing the don't care entries in the vectors of the test set for single fault detection, 100% and nearly 100% fault coverages can be achieved under the MFSM and SFMM models respectively.

Effectiveness of single fault tests to detect multiple faults in parity trees

As fabricated circuitry becomes larger and denser, the modern industrial automatic test pattern generation techniques, which focus on the detection of single faults, become more likely to overlook multiple (simultaneous) faults. Although there are exponentially more multiple faults than single faults in any given circuit design, only a few additional test patterns are needed to cover all of the multiple faults, if the test generation starts from the complete test set for single faults. In this paper, we first show the case where test patterns for single faults are sufficient to cover all multiple faults, and then explain in which conditions some of the multiple faults may be overlooked. Based on this analysis, we propose a method that can efficiently generate the complete test set for double faults without traversing all the faults. Since most of the double faults can be detected by the single faults' test set, the proposed method only selects the uncovered double faults by analyzing the propagation paths of single faults, and then generating new test patterns only for those uncovered faults. The experimental results show that based on the single faults' test set, the proposed method only needs to create a small number of additional test patterns to cover all double faults in most of the given circuits. By repeating the same process, the proposed method can be incrementally applied to deal with all multiple faults.

In combinational logic circuits the generation of complete fault detection test sets requires the determination of the complete test sets of all possible stuck-at faults. In this study, an efficient procedure is developed for finding all the complete test sets of all possible single stuck-at faults in a combinational circuit. The developed procedure primarily uses the properties of logic gates. An example is solved by the use of the developed procedure.

The fabricated circuitries are getting massive and denser with every passing year due to which a normal automatic test pattern generation technique to detect only the single stuck-at faults will overlook the multiple stuck-at faults. But generating test patterns that can detect all possible multiple stuck-at fault is practically not possible. Hence, this paper proposes a method, where multiple faults can be detected by using test vectors for detecting single stuck-at faults. Here, the patterns for detecting single faults are generated and their ability to detect multiple stuck-at faults is also analyzed. From the experimental results it was observed that, the generated vectors for single faults cover maximum number of the multiple faults and then new test vectors are generated for the undetermined faults. The generated vectors are optimized for the compact test patterns in order to reduce the test power.

Due to the continuous shrinking of semiconductor technology, there are more and more subtle errors or faults widely distributed in manufactured chips, and traditional "single" stuck-at fault model may become inappropriate. It is definitely better if all combinations of multiple faults can be completely tested. In this paper, we present ATPG (Automatic Test Pattern Generation) techniques targeting all multiple stuck-at faults, i.e. all combinations of stuck-at faults. That is, given "n" possibly faulty locations in a circuit, the target set of faults consists of 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> - 1 fault combinations, as each possibly faulty location is under stuck-at 1, stuck-at 0, or normal/non-faulty. Traditional ATPG flows use fault simulators to eliminate all detectable faults by the current set of test vectors. The problem, however, fault simulators represent fault lists explicitly in the sense that all possible faults are enumerated in the fault lists. This prevents us from dealing with ultra large fault lists, such as 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> - 1 faults. We need "implicit" representation of faults in order to deal with such huge numbers of faults or fault combinations. We present SAT based formulations for ATPG of circuits having very large numbers of faults by implicitly eliminating detected faults. We solve a set of SAT problems whose constraints increase pure incrementally (here "pure" means never deleting constraints), and so the entire solving process can be very efficient, as all learnings obtained so far are valid in the following SAT problems. Experiments are performed on combinational parts of ISCAS89 circuits in their AIG (AND-Inverter Graph) representations. We have successfully generated the complete set of test vectors assuming that faults happen only at outputs of gates. Our ATPG techniques can also start with a given set of test vectors. If we start the ATPG processes with a set of test vectors for single stuck-at faults, we can obtain the set of additional test vectors required for multiple stuck-at faults. Results are a little bit surprising in the sense that we need very few additional test vectors for multiple faults, although the numbers of fault combinations are exponentially larger. As far as we know, for the first time, complete test vectors for all stuck-at faults for ISCAS89 circuits where faults happen only at outputs of gates in AIG representations of the circuits have been obtained.

Test generation procedures target a variety of fault models in order to produce test sets that are effective for defect detection. This paper considers the likely scenario where two-cycle skewed-load tests are generated to detect single transition faults, and the test set is complemented with tests for single stuck-at faults that are not detected by the transition fault test set. For this scenario, this paper makes several unique observations that can be utilized to produce a single compact test set that consists only of two-cycle skewed-load tests for both fault models. The first observation is that a single-cycle test for a stuck-at fault can be transformed into a skewed-load test that is guaranteed to detect the stuck-at fault without performing logic or fault simulation. The second observation is that skewed-load tests, which are transformed from single-cycle tests for stuck-at faults, sometimes detect more transition and stuck-at faults than tests that were generated for transition faults. The third observation is that a static test compaction procedure, which is based on the modification and removal of tests, is effective in this context because it allows tests for stuck-at faults to detect more transition faults and vice versa. This paper describes a test compaction procedure based on these observations and presents experimental results for benchmark circuits to demonstrate the effectiveness of the procedure.

This paper deals with two important related problems in the area of detection of single faults in combinational logic networks. The first is to determine the different equivalence classes of all possible single faults in the given network and this has been achieved by introducing the concept of a new typo of fault graph. Algorithms have been developed to construct the fault graph of a given combinational network from the fault graphs of the component gates and to enumerate the equivalence classes of faults from the fault graph of the network. The second problem, dealt with in this paper, is to enumerate the minimal complete test set to detect single faults in the network and this has been carried out by utilizing the concept of boolean difference in a new manner, so that the computational complexity has been greatly reduced compared to the existing procedures of fault detection by boolean difference

Applications of reversible circuits can be found in the fields of low-power computation, cryptography, communications, digital signal processing, and the emerging field of quantum computation. Furthermore, prototype circuits for low-power applications are already being fabricated in CMOS. Regardless of the eventual technology adopted, testing is sure to be an important component in any robust implementation.

The presence of an undetectable fault <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ui</i> may modify the response of a detectable fault <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dj</i> to a test set used for fault diagnosis. This may impact the accuracy of fault diagnosis based on the responses of single faults. Many state-of-the-art diagnosis processes are based on the responses of single stuck-at faults even though their goal is to diagnose defects (including multiple defects) that are different from stuck-at faults. Therefore, we study the effects of undetectable single stuck- at faults on the accuracy of fault diagnosis based on the responses of single stuck-at faults. For this purpose, we consider the cases where the response of a double stuck-at fault <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ui</i> & <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dj</i> , which consists of an undetectable fault <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ui</i> and a detectable fault <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dj</i> , is different from the response of the single fault <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dj</i> . We show that there are significant, yet manageable, numbers of such faults in benchmark circuits under test sets used for fault diagnosis. In all these cases, a fault diagnosis process based on single stuck-at faults may not identify the locations of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dj</i> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ui</i> as candidate defect sites if a defect affects the sites of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dj</i> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ui</i> . We conclude that it is important to consider <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ui</i> & <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dj</i> during fault diagnosis in order not to preclude the sites of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dj</i> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ui</i> as candidate defect sites.

An attempt is made to demonstrate that the problem of complete test set generation is amenable to the problem of pseudo-Boolean programming. For this purpose, various types of faults, viz., single faults, multiple faults, and bridging faults, are considered. The key issue is to obtain logical expressions for the primary output line in terms of different faulty internal nodes to find real transforms. Using standard rules, the real transforms of a Boolean function can be obtained directly without any algebraic manipulation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In this paper a hierarchical structure of fuzzy neural networks (FNNs) and how to train it for fault isolation given an appropriate data patterns, are presented. Fault symptoms concerning multiple simultaneous faults are harder to learn than those associated with single faults. Furthermore, the larger the set of faults, the larger the set of fault symptoms will be and, hence, the longer and less certain the training outcome. In order to overcome this problem, the proposed approach has a hierarchical structure of three levels where several FNNs are used. Thus, a large number of patterns are divided into many smaller subsets so that the classification can be carried out more efficiently. One of the advantages of this approach is that multiple faults can be detected in new data even if the network is trained only with data representing single abrupt faults. A continuous binary distillation column having several actuated valves with PID loops has been used as test bed for the proposed approach.

Fault Diagnosis is a critical process to identify the locations of physical defects in advanced integrated circuits. Current diagnosis tools often report multiple types of faults as defect candidates. Thus an efficient method to distinguish different types of faults is highly desired. Stuck-at and bridging faults are two most commonly used DC fault models during diagnosis. In this paper we present an efficient diagnosis pattern generation procedure to distinguish stuck-at faults and bridging faults. Two major techniques are proposed. The first one is a fault-inactivation method (FIM) that can quickly distinguish most fault pairs by inactivating one fault while detecting the other in each fault pair. The second one is a fault-types-transformation method (FTTM) that can transform the problem of distinguishing a stuck-at fault and a bridging fault into the problem of detecting a stuck-at fault. Both methods involve only one copy of the original circuit and require only an ordinary ATPG tool for stuck-at faults. Furthermore, both methods can deal with multiple fault pairs at a time and thus not only is the required CPU time small but also the dynamic test compaction capability of the ATPG tool can be utilized. Experiments on a large number of randomly selected fault pairs in ISCAS'89 and IWLS'05 benchmark circuits have been carried out. The results show that the FIM can distinguish about 91.9% of distinguishable fault pairs quickly and the FTTM can distinguish all other distinguishable fault pairs and identify all equivalent fault pairs. The average ratio of the number of diagnosis patterns over that of the test patterns for stuck-at faults is only 0.64. On average, one diagnosis pattern can distinguish 10.89 fault pairs.

The present work focuses on a test design with self correcting features and with much higher efficiency for L1 cache modules. It is based on 2-state 3-neighborhood cellular automata (CA). The design ensures identification of the region of defective cache module in the Chip Multiprocessors (CMPs) and can memorize the fault while continuing with the test. Exploration of 3-neighborhood CA theory further strengthens the design towards a fault tolerant test structure. Self correction of the single stuck-at fault as well as the multiple stuck-at faults in the test structure has been envisaged. This fault tolerant test hardware achieves 100% accuracy in testing for single stuck-at fault whereas, the accuracy for multiple stuck-at faults is found to be 22%. As the design is developed around the 3-neighborhood CA, it becomes simpler as well as cheaper while considering VLSI implementation than that of the 5-neighborhood CA based design proposed in the literature.