NBTI-aware power gating design

Negative Bias Temperature Instability (NBTI) has been regarded as most important source of reliability of CMOS devices, and specifically pMOS transistors.In this work we focus on the NBTI-induced degradation of sleep transistor cells More in details we present a practical SPICE-based analysis framework for evaluating delay degradation of power-gated circuits due to NBTI-induced current capability reducing of pMOS sleep transistor. We also describe three NBTI-tolerant pMOS sleep transistor cell design approaches, in which the Vi>th increase due to NBTI is compensated through (i) sleep-transistor over-sizing, (ii) forward-body-biasing, (iii) equivalent 0-probability reduction of the sleep-transistor driving signal.Characterization results on a commercial 45nm CMOS technology define fundamental guide-lines to be used during NBTI-aware sleep-transistor design, while experiments on an industrial benchmark highlight the importance of considering NBTI effect on pMOS sleep transistor design, emphasizing the effectiveness of the proposed design methodologies: more than 85% of time-life extension.

The wake-up process of a power-gated design may induce an excessive surge current and threaten the signal integrity. A proper wake-up sequence should be carefully designed to avoid surge current violations. On the other hand, PMOS sleep transistors may suffer from the negative-bias temperature instability (NBTI) effect which results in decreased driving current. Conventional wake-up sequence decision approaches do not consider the NBTI effect, which may result in a longer or unacceptable wake-up time after circuit aging. Therefore, in this paper, we propose a novel NBTI-aware wake-up strategy to reduce the average wake-up time within a circuit lifetime. Our strategy first finds a set of proper wake-up sequences for different aging scenarios (i.e. after a certain period of aging), and then dynamically reconfigures the wake-up sequences at runtime. The experimental results show that compared to a traditional fixed wake-up sequence approach, our strategy can reduce average wake-up time by as much as 45.04% with only 3.7% extra area overhead for the reconfiguration structure.

The life time of RF front end in wireless sensor networks (WSN) is so important that it decides whether the whole system can work normally for a long time. Under CMOS technology, negative bias temperature instability (NBTI) is one of the most important factors that decide chips' life time. Especially with the feature size declining, NBTI effect is becoming more and more serious. Previous works mainly focus on NBTI effect at device level, or NBTI effect in large-scale digital circuits. In this paper, for the WSN node, we study the NBTI impact on the front- end circuits, such as voltage-controlled oscillators (VCO), charge pump (CP), low noise amplifier (LNA), and the whole transceiver system. The circuit level NBTI degeneration models are built for the key modules and the entire transceiver. The mathematical models can be summarized into a conclusion that the phase noise of the VCO will deteriorate, the current mismatch of the CP and the noise figure of the LNA will both increase, and then the sensitivity and adjacent channel selectivity (ACS) will be depressed by NBTI. Under HJTC 0.18-mum technology, our conclusions are proved by the simulation results.

Power Gating is effective for reducing leakage power. Previously, a Distributed Sleep Transistor Network (DSTN) was proposed to reduce the sleep transistor area by connecting all the virtual ground lines together to minimize the Maximum Instantaneous Current (MIC) through sleep transistors. In this paper, we propose methodologies for determining the size of sleep transistors of the DSTN structure considering charge-balancing effect. We also introduce a new relationship among MIC, IR drops and sleep transistor networks from a temporal viewpoint and improve the sizing results. Our methods achieve significant better results than previous works.

Power-gating (PG) techniques have been widely used in modern digital ICs to reduce their standby leakage power during idle periods. Meanwhile, virtual supply voltage (VVDD) of a power-gated IC is a function of strength of a PG device and total current flowing through it. Thus, the VVDD level becomes susceptible to 1) negative bias temperature instability (NBTI) degradation that weakens the PG device over time and 2) temporal temperature variation that affects active leakage current (thus total current) of the IC. To account for the NBTI degradation, the PG device must be upsized such that it guarantees a minimum VVDD level that prevents any timing failure over chip lifetime. Moreover, the PG device is also sized for the worst-case voltage drop partly resulted by a large amount of active leakage current at high temperature. However, increasing the size of the PG device to consider both effects leads to higher VVDD (thus active leakage power) than necessary at low temperature and/or in early chip lifetime. To minimize active leakage power increase due to these effects, we propose two techniques that adjust strength of a PG device based on its usage and IC's temperature at runtime. Both techniques are applied to an experimental setup modeling total current consumption of an IC in 32nm technology and their efficacy is demonstrated in the presence of within-die spatial process and temperature variations. On average of 100 die samples, they can reduce active leakage power by up to 10% in early chip lifetime.

In this chapter, modelling of Negative Bias Temperature Instability (NBTI), how it is incorporated with Static Random Access Memory (SRAM) and its impact on different SRAM cache configurations is presented. Investigations of how NBTI affects different power saving cache strategies employing the standard symmetric and asymmetric 6-transistor (6T) SRAM, and the isolated read-port 6T SRAM bitcells, are presented. It is observed that more than 38–66% of the recovery in stability parameters (SNM and WNM) under different power saving cache strategies have been achieved for different SRAM bitcells based cache configurations. It is also found that the low V TH transistors age faster than the high V TH transistors due to NBTI. Hence, NBTI effect is more pronounced in future technologies due to reduction in V TH with technology scaling. Also NBTI effect is more significant at higher temperature.

The tremendous scaling of the semiconductor devices is producing the high-density integrated circuits (ICs). Metal-oxide-semiconductor field-effect transistors (MOSFETs) are the basic building blocks for the ICs. The lower area requirement with increased numbers of devices on a substrate makes it an interesting field of very-large-scale integration (VLSI) design. The reliability of the logic circuits is the concern issue in modern-era electronics. Reliability affects the overall performance of the logic circuits and possibility to the failure of the semiconductor devices. Negative bias temperature instability (NBTI) degradation is the major concern in ultra-deep submicron (DSM) regime. The negative threshold voltage of PMOS device when shifted in NBTI effect causes performance degradation over the time. NBTI degradation is the aging effect for PMOS device. This chapter presents the overview of NBTI effect and its possible solution.

Negative bias temperature instability (NBTI) in PMOS transistors has become a significant reliability concern in present day digital circuit design. With continued scaling, the effect of NBTI has rapidly grown in prominence, forcing designers to resort to a pessimistic design style using guard-banding. Since NBTI is strongly dependent on the time for which the PMOS device is stressed, different gates in a combinational circuit experience varying extents of delay degradation. This has necessitated a mechanism of quantizing the gate-delay degradation, to pave the way for improved design strategies. Our work addresses this issue by providing a procedure for determining the amount of delay degradation of a circuit due to NBTI. An analytical model for NBTI is derived using the framework of the reaction-diffusion model, and a mathematical proof for the widely observed phenomenon of frequency independence is provided. Simulations on ISCAS benchmarks under a 70nm technology show that NBTI causes a delay degradation of about 8% in combinational logic based circuits after 10 years (ap 3 times 108s)

A new on-line methodology is used to characterize the negative bias temperature instability (NBTI) without inherent recovery. Saturation drain voltage shift and mobility shift are extracted by ID−VD characterizations, which were measured before stress, and after every certain stress phase, using the proportional differential operator (PDO) method. The new on-line methodology avoids the mobility linearity assumption as compared with the previous on-the-fly method. It is found that both reaction–diffusion and charge-injection processes are important in NBTI effect under either DC or AC stress. A similar activation energy, 0.15 eV, occurred in both DC and AC NBTI processes. Also degradation rate factor is independent of temperature below 90°C and sharply increases above it. The frequency dependence of NBTI degradation shows that NBTI degradation is independent of frequencies. The carrier tunnelling and reaction–diffusion mechanisms exist simultaneously in NBTI degradation of sub-micron pMOSFETs, and the carrier tunnelling dominates the earlier NBTI stage and the reaction–diffusion mechanism follows when the generation rate of traps caused by carrier tunnelling reaches its maximum.

In this work, we have correlated the degradation by Negative Bias Temperature Instability (NBTI) in MOS Junctionless Nanowire Transistors (JNTs) to the electric field inside the devices. We have measured samples with doping concentrations of 1×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> , biased at two different drain voltages, with several channel lengths (L) and widths (W). To extend the analysis, aiming at the understanding the physical behavior of the devices, we performed simulations of NBTI considering devices with similar characteristics. As a result, a higher degradation by the NBTI effect was obtained for the JNTs with lower doping concentration and shorter channel. The behavior of the NBTI has been correlated to the electric field of the devices and it is shown that the electric field becomes important mainly in accumulation regime.

Power gating technique reduces leakage power in the circuit. However, power gating leads to large voltage fluctuation on the power rail during power gating mode to active mode due to the package inductance in the Printed Circuit Board. This voltage fluctuation may cause unwanted transitions in neighboring circuits. In this work, a power gating architecture is developed for minimizing power in active mode and noise is analyzed. The effect of different noise minimization approaches for reducing power supply noise is evaluated in power gating architecture. A new concept of noise minimization technique using Low Dropout Voltage regulator is proposed in this paper. The amount of charge in the internal nodes of the power gating circuit passes through the sleep transistors during the wake-up transition is controlled by the proposed noise minimization techniques. The Low Dropout Voltage Regulator is designed newly in such a way that can be used to reduce bounce noise by minimizing voltage fluctuation on the power rail of power gating circuit. Architectures have been developed in Synopsys Custom Designer tool at iPDK 90nm technology. Percentage saving of noise on the power supply is reduced up to 99%.

Negative Bias Temperature Instability (NBTI) is considered one of the major reliability concerns of transistors in current and upcoming technology nodes and a main cause of their diminished lifetime. We propose a new means to mitigate the effects of NBTI on SRAM-based register files, which are particularly vulnerable due to their small structure size and are under continuous voltage stress for prolonged intervals. The conducted results from our technology simulator demonstrate the severity of NBTI effects on the SRAM cells - especially when process variation is taken into account. Based on the presented analysis, we show that NBTI stress in different registers needs to be tackled using different strategies corresponding to their access patterns. To this end, we propose to selectively increase the resilience of individual registers against NBTI. Our technique balances the gate voltage stress of the two PMOS transistors of an SRAM cell such that both are under stress for approximately the same amount of time during operation - thereby minimizing the deleterious effects of NBTI. We present mitigation implementations in both hardware and in software along with the incurred overhead. Through a wide range of applications we can show that our technique reduces the NBTI-induced reliability degradation by 35% on average. This is 22% better than current State-of-the-Art.

Hardware trojans in 3-D ICs due to NBTI effects and countermeasure

System-on-a-chip with multiple power domains reduces leakage power consumption by power gating which shut off the idle blocks. Power gating is an effective technology to reduce sub-threshold leakage current. However, without good understanding and careful design, negative effects of power gating may overwhelm the potential gain and make the technique not worth the effort. For example, power gating may cause instantaneous current when sleep transistors are turned on. And instantaneous current will lead to VDD voltage drop, ground bounce, and inductive noise in power supply line. To reduce the ground bounce, we proposed new power gating structures with added bulk controller when sleep transistors are turned on. Simulation results show that the maximum voltage fluctuations for our power gating structures are smaller than those for the other power gating structures. Our power gating structures reduce the instantaneous current and voltage fluctuations in the power supply line.

Leakage power reduction in nano-CMOS designs has gained tremendous interest both in academia and industry. Many techniques have been proposed in the literature for leakage power reduction and one of the prominent techniques for leakage power reduction is the use of sleep transistors as power-gating elements to cut-off sub-threshold leakage current in circuits when they are in stand-by mode. Although sleep transistor insertion is very effective in cutting-off leakage, it also incurs timing, area and routing overhead. Since most of the sleep transistor insertion methodologies do post layout insertion, care should be taken such that there is minimal perturbation of the original layout. Over design of sleep transistors cells and sub-optimal sleep transistor placement must be avoided to achieve final design closure. Since the sleep transistor area plays an important and prominent role in this aspect, it necessitates for optimal sleep transistor sizing and synthesis technique under area constraints. In this paper, we first provide a methodology for optimal sleep transistor synthesis under given area constraints. We then apply our technique to the general timing and area constraint driven row-based power-gating methodology proposed in [13] and show how optimal low leakage designs with constraints on timing and area can be designed.