New materials for post-Si computing: Ge and GeSn devices

This article presents an integrated current mode configurable analog block (CAB) system for field-programmable analog array (FPAA). The proposed architecture is based on the complementary metal-oxide semiconductor (CMOS) transistor level design where MOSFET transistors operating in the saturation region are adopted. The proposed CAB architecture is designed to implement six of the widely used current mode operations in analog processing systems: addition, subtraction, integration, multiplication, division, and pass operation. The functionality of the proposed CAB is demonstrated through these six operations, where each operation is chosen based on the user’s selection in the CAB interface system. The architecture of the CAB system proposes an optimized way of designing and integrating only three functional cells with the interface circuitry to achieve the six operations. Furthermore, optimized programming and digital tuning circuitry are implemented in the architecture to control and interface with the functional cells. Moreover, these designed programming and tuning circuitries play an essential role in optimizing the performance of the proposed design. Simulation of the proposed CMOS Transistor Based CAB system is carried out using Tanner EDA Tools in 0.35 μm standard CMOS technology. The design uses a V power supply and results in maximum 3 dB bandwidth of 34.9 MHz and an approximate size of 0.0537 . This demonstrates the advantages of the design over the current state-of-the-art designs presented for comparison in this article. Consequently, the proposed design has a clear aspect of simplicity, low power consumption, and high bandwidth operation, which makes it a suitable candidate for mobile telecommunications applications.

The scaling limit of Si-based complementary metal oxide semiconductor (CMOS) transistors is approaching. The performance enhancement can no longer be guaranteed due to intrinsic mobility issues of silicon. The considerably higher charge carrier mobility of III-V compound semiconductors and Ge has led to renewed interest as these materials are considered for the development of transistors for 7 nm and 5 nm technology nodes [1-3]. Wet-chemical etching for surface and interface processing has proven to be effective for reducing defectivity. Due to the aggressive downscaling of transistors an ultimate etching selectivity and control at the nanometer and atomic-layer scale is required. Therefore, a thorough understanding of the interactions between the substrate and the solution (both chemical and electrochemical) is essential. In this work the etching kinetics of (100) III-As are discussed for various HCl/H2O2 compositions in the low pH range. The etch rates were determined by measuring the total amount of dissolved material with Inductively Coupled Plasma – Mass Spectrometry [4]. Electrochemical impedance measurements were performed to determine the band energetics of InGaAs during etching for various HCl/H2O2compositions. III-As can be etched in HCl solution in the presence of an oxidizing agent. In a first step the surface bonds are oxidized by H2O2. The formed III-As (hydr)oxides are subsequently dissolved by the acid. Fig. 1 shows the influence of the HCl concentration on the etch rate for InGaAs in 0.02 M H2O2 solution. For <0.01M HCl the oxide solubility controls the etch rate. For >0.01M HCl the dissolution kinetics are controlled by the wetting properties (i.e. surface termination): the etch rate decreases with increasing hydrophobicity. It was demonstrated that this is due to Cl-termination. The trend is comparable for GaAs and InAs [5, 6]. Electrochemical impedance measurements for InGaAs suggest that Cl termination results in a significant shift in flat-band potential (EFB) as shown in Fig. 1. The observed change in the band energetics has an important consequence for the dissolution mechanism of InGaAs. It can be shown that the mechanism for 0.01M HCl is both chemical and electrochemical, while for 1M HCl dissolution is mainly chemical. Such insight can, for instance, be used to influence the surface stoichiometry: suppressing the electrochemical mechanism lowers the build-up of elemental As0: InGaAs + 3h+ (VB) => In3+ + Ga3+ + As0 Fig. 2 shows the etch rate of Ge (100) as function of the H2O2 concentration for 1M and 6M HCl. Interestingly, the etching kinetics for Ge are also strongly influenced by the wetting properties. For 1M HCl, the surface ishydrophilic and the etch rate increases from <0.1 nm/min to 21 nm/min in the range 0-50 mM H2O2. When the HCl concentration is increased to 6M, the surface becomes hydrophobic and the etch rate is lowered. These results suggests that Cl-termination is also important for the dissolution mechanism of Ge. Due to the low solubility of Ge suboxides [7], higher HCl concentrations are required to render the surface hydrophobic during etching.

Metal gate technology for nanoscale transistors—material selection and process integration issues

Operational Transconductance Amplifiers (OTAs) are the most pivotal blocks in analog circuits and systems. With the emersion of catastrophic short channel effects for Complementary Metal Oxide Semiconductor (CMOS) transistors at deep nanometric regime, the microelectronics scientists have focused on designing ultra-miniature OTAs based on non-silicon materials. During the last few years, Gate-All-Around Carbon Nanotube Field Effect Transistors (GAA-CNTFETs) with astonishing electrical and physical properties have drawn extensive attention of nanoelectronics researchers as a potential platform to represent high-performance nanoscale OTAs. In this regard, this work aims to propose an ultra-miniature ultra-wideband OTA based on the 10 nm GAA-CNTFET technology node. The proposed OTA benefits from the ballistic transport operation of the GAA-CNTFET transistors at ultra-scaled dimensions which provide a superior bandwidth (2.88 GHz) along with suitable power consumption (44.8 $$\upmu$$ W). The proposed OTA shows a 64.5 dB open-loop gain and a 59 dB common-mode rejection ratio at a 1 V supply voltage. Moreover, due to the utilization of the indirect feedback compensation method, the proposed GAA-CNTFET-based OTA presents an appropriate phase margin (61 $$^{\circ }$$ ) with a smaller compensator capacitor. With the mentioned performance metrics and occupying only 0.198 $$\upmu {\mathrm{m}^{2}}$$ physical area, the proposed GAA-CNTFET OTA has the potential to be considered as a replacement for nanoscale CMOS-based OTAs.

Computational logic, in the form of semiconductor chips of the complementary metal oxide semiconductor (CMOS) transistor structure, is used in personal computers, wireless devices, IT network infrastructure, and nearly all modem electronics. This study provides a life-cycle energy analysis for CMOS chips over 7 technology generations with the purpose of comparing energy demand and global warming potential (GWP) impacts of the life-cycle stages, examining trends in these impacts over time and evaluating their sensitivity to data uncertainty and changes in production metrics such as yield. A hybrid life-cycle assessment (LCA) model is used. While life-cycle energy and GWP of emissions have increased on the basis of a wafer or die, these impacts have been reducing per unit of computational power. Sensitivity analysis of the model shows that impacts have the highest relative sensitivity to wafer yield, line yield, and die size and largest absolute sensitivity to the use-phase power demand of the chip.

An application-specific integrated circuit (ASIC) for a high reliability application is found to have a missing sidewall spacer in a single transistor. Manufacturer burn-in and standard component electrical tests do not capture this defect. The defect manifests after exposure to ionizing radiation. Photon emission microscopy (PEM), laser voltage imaging (LVI), and laserassisted device alteration (LADA) are used to isolate the failure site. At the failure site a focused ion beam (FIB) cross section indicates that a doubly doped drain (DDD) (N+) is likely present where a lightly doped drain (LDD) is designated. This defect leads to a failure mode that is consistent with hot-carrier injection in complementary metal-oxide semiconductor (CMOS) transistors. This paper presents the testability from a fault isolation aspect, shmoo plot characterization, and backside optical techniques to identify its spatial location. A discussion of the results includes why ionizing radiation allowed the defect’s capture and potential implications of using ionizing radiation as a viable failure analysis technique.

This paper presents a new programmable universal filter and quadrature oscillator based on single output operational transconductance amplifiers (OTAs). The proposed universal filter and quadrature oscillator can be achieved into single topology by programming using analog switches. When the circuit programs as a universal filter, it can realize low-pass, high-pass, band-pass, band-stop and all-pass filters with orthogonal and electronic controls of the natural frequency and the quality factor. When the circuit programs as a quadrature oscillator, it provides three-phase quadrature output signals which the condition of oscillation and the frequency of oscillation can be controlled orthogonally and electronically. The proposed structure can be realized based on single output OTAs which is easily implemented both commercially available integrated circuits as OTAs and complementary metal-oxide semiconductor and bipolar junction transistor OTA as IC forms. The performance of the proposed circuit is investigated by SPICE simulation using standard 0.18 μm CMOS process and experiment test using LM13600 discrete component integrated circuit as OTAs is used to confirm the workability of the new circuit.

Data converters are necessary for the conversion process of analog and digital signals. Successive approximation register (SAR) analog-to-digital converters (ADC) can achieve high levels of accuracy while consuming relatively low amounts of power and operating at relatively high speeds. This paper describes a design of 8-bit 125 kS/s SAR ADC with a proposed high-speed comparator design based on dynamic latch architecture. The proposed design of the comparator enhances the performance compared to a conventional dynamic comparator by adding two parallel clocked input complementary metal-oxide semiconductor (CMOS) transistors which reduce the parasitic resistance in the latch ground path and serve to minimize the latch delay time. The design of each sub-system for the ADC is explained thoroughly, which contains a sample and hold circuit, successive approximation register, charge redistribution types digital-to-analog converter, and the new proposed comparator. The proposed design is implemented using 180 nm CMOS technology with a power supply of 1.2 V. The average inaccuracy in differential non-linearity (DNL) is +0.6/−0.8 LSB (least significant bit), and integral non-linearity (INL) is +0.4/−0.7 LSB. The proposed design exhibits a delay time of 157 ps at 1 MHz clock frequency.

After years of doping, straining, shrinking, and tweaking, engineers seem to have exhausted all their strategies for improving the planar complementary metal-oxide semiconductor (CMOS) transistors at the heart of today's computer processors. Producers of cutting-edge chips are now resorting to new structures- building up in three dimensions or constructing transistors in ultrathin layers of silicon-to ensure that devices keep shrinking and that Moore's Law keeps going just a bit longer.

We propose a complementary self-biasing method which enables the single-electron transistor (SET)/complementary metal-oxide semiconductor (CMOS) hybrid multi-valued logics (MVLs) to operate well at high temperatures, where the peak-to-valley current ratio (PVCR) of the Coulomb oscillation markedly decreases. The new architecture is implemented with a few transistors by utilizing the phase control capability of the sidewall depletion gates in dual-gate single-electron transistors (DGSETs). The suggested scheme is evaluated by a SPICE simulation with an analytical DGSET model. Furthermore, we have developed a new process technology for the SET/CMOS hybrid systems. We have confirmed that both of the fabricated devices, namely, SET and CMOS transistors, exhibit the ideal characteristics for the complementary self-biasing scheme: the SET shows clear Coulomb oscillations with a 100 mV period and the CMOS transistors show a high voltage gain.

Homogeneous Si0.5Ge0.5 bulk crystal growth as substrates for strained Ge thin films by the traveling liquidus-zone method

The Semiconductor Industry Association (SIA) expectations are to achieve the 22nm technology at the end of 2018. So aggressively continuation in physical size scaling of Complementary Metal Oxide Semiconductor Transistor (MOSFET) experiences difficulties due to various factors. The conventional oxide can be scaled down to two atomic layers of about 7 A˚ because of limitations of leakage current, interface trap densities, and limitations of statistical parameters of fabrications. This paper addresses the main challenges and analyzes of the critical issues of MOS gate dielectric in nanometer range and provides an alternate material. So MOS capacitors were fabricated with and TiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> / SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> as dielectric material on P-type silicon wafers and characterized for microelectronics application. TiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> films were characterized using XRD, Capacitance-voltage (C-V) and Current-voltage (I-V) measurements. The measured results show that TiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> /SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> dielectric layer has desirable properties compared to TiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> films grown by DC magnetron sputtering.

To ensure reliability inside complementary metal oxide semiconductor transistors, the results on the basis of negative bias temperature instability by incorporating aged TiO2 gels on SiO2 dielectric have been reported. TiO2 was chosen for the incorporation. Precursor aging has been carried out for 2, 3 and 4 days. Samples with maximum dielectric constant after aging and UV treatment were extracted. Under DC stress, exploiting cured sample (4 days aged and 3 h UV exposed) of TiO2 results in a 70% (70% decrease in threshold voltage) increase in drain current. Under AC or dynamic bias stress, exploiting cured sample (4 days aged and 3 h UV exposed) of TiO2 results in a 65% increase (65% decrease in threshold voltage).

This paper investigate the impact of CMOS (complementary metal-oxide-semiconductor) gate microstructure on the reliability and performance of deep-submicrometer CMOS transistors. The amorphous silicon (/spl alpha/-Si) gate provides better capability for suppression of boron penetration in p/sup +/ doped gate p-channel MOSFETs, but gate depletion in the /spl alpha/-Si gate is slightly more severe than that of the poly-Si gate. The gate-length-dependent gate-depletion effect, in which the difference in linear g/sub m/ between MOSFETs with two different gate microstructures shows a strong L/sub g/-dependence, is reported and interpreted by impurity diffusion along the grain boundary. A gate nitrogen implant as an effective method for suppression of the boron diffusion is also discussed with emphasis on the impact on both device reliability and performance.

The work function of polycrystalline nickel silicide film formed by rapid thermal annealing (RTA) has been studied using capacitance-voltage (C-V) measurements and metal-oxide semiconductor (MOS) structures. The effect of sintering temperature on work function has also been studied. Results show that the work function of NiSi gate is about 4.6 eV and is stable from 400 to 800°C. For NiSi gate, the work function is 5 eV. The gate-substrate leakage current is small and the oxide quality is similar to that in Al-gate MOS capacitors even for oxides as thin as 8 nm. The poly-gate depletion effect (PDE) has also been investigated by quasi-static C-V. Compared with that of poly-Si and no PDE is observed in silicide-gate n-MOS device even when the gate is undoped. The results suggest that nickel silicide film may be used as a potential gate material in complementary MOS or thin-film transistor devices. © 2001 The Electrochemical Society. All rights reserved.