Enhancing Point Defect Isolation by Using Ionizing Radiation

Abstract

Hot-carrier (HC) degradation phenomena in p-channel lightly doped drain (LDD) MOSFETs and the effects of an LDD structure in minimizing HC degradation are described. Hot-electron injection in p-channel LDD MOSFETs causes effective channel length shrinkage. This phenomenon is also observed in conventional p/sup +/-drain MOSFETs but differs greatly from that in n-channel LDD MOSFETs. This is because hot electrons trapped in gate SiO/sub 2/ accumulate carriers (holes) along the channel region near the drain and decrease the pinchoff region. On the other hand, the LDD region in p-channel MOSFETs reduces HC generation to one-tenth of that in p/sup +/-drain MOSFETs under the same applied voltage. Moreover, the lifetimes of the LDD MOSFETs defined as how long it takes the transconductance deviation to reach 10% are longer by two orders of magnitude than those of the p/sup +/-drain MOSFETs under the same HC generation conditions. To obtain the best lifetime, it is shown that the optimum boron dose in the LDD region is between 1 and 3*10/sup 13/ cm/sup -2/. >

Thermal Laser Stimulation (TLS) is employed extensively in semiconductor device fault isolation techniques such as TIVA (Thermal Induced Voltage Alteration), OBIRCH (Optical Beam Induced Resistance Change), SDL (Soft Defect localization), CPA (Critical Parameter Analysis), LADA (Laser Assisted Device Alteration), and LVI (Laser Voltage Imaging), etc. To investigate the TLS effects on 7nm FinFET transistor parameters, several transistors of 7nm FinFET inline ET (Electrical Test) macros were tested while employing TLS of various energy values. The test was done in linear mode so that the joule heating caused by the electrical current would be minimized. The experimental results showed that both NFETs and PFETs experienced increased Ioff (Off current) and Sub_Vt_lin_slope (Subthreshold slope), and decreased Ion (On current) and Vt_lin (Threshold voltage) due to elevated temperature of the transistor from TLS. Higher laser power caused greater effects on transistor parameters. The temperature increase on a transistor by TLS depends on the amount of laser energy transferred to, absorbed by, and dispersed by the transistor area. Factors such as the efficient coupling of the SIL (Solid Immersion Lens) with the Silicon backside surface, the transistor size, and the local layout around the transistor will greatly affect the amount of heat delivered to a particular transistor, even while using the same laser power. Thus, setting the laser power for fault isolation with TLS should consider these factors. Our experimental results also showed that the alteration of transistor parameters under TLS was not permanent if the laser power was carefully selected. It should be noticed that during dynamic fault isolation, a transistor may be switching between off, linear mode, and/or saturation mode. The temperature increase on the transistor under TLS may be higher than anticipated due to joule heating if the transistor operation is not confined to the linear region only. Experiments on transistors operating in saturation mode under TLS can be the subject of future work. The results obtained from these experiments can still establish guidelines for laser power settings to be used in the related fault isolation techniques for devices manufactured at the 7nm node so as to achieve non-destructive fault isolation.

This presentation provides an overview of photonic measurement techniques and their use in isolating faults and locating defects in ICs. It covers transmission, reflectance, and absorption methods, describing key interactions and important parameters and equations. Reflectance methods discussed include electro-optical probing (EOP), electro-optical frequency modulation (EOFM), and laser-voltage imaging (LVI). Absorption methods covered include those based on the absorption of light in semiconductors, as in optical beam induced current (OBIC), light-induced voltage alteration (LIVA), and laser-assisted device alteration (LADA), and those based on absorption in metals, as in thermally induced voltage alteration (TIVA), optical beam induced resistance change (OBIRCH), and thermoelectric voltage generation or Seebeck effect imaging (SEI). The presentation also covers thermoluminescence (lock-in thermography) and electroluminescence (photon emission) measurement methods and assesses hardware security risks posed by current and emerging photonic localization techniques.

A novel method of determining the spatial distribution of interface states of MOS transistors by charge pumping measurement has been developed. Unlike other existing methods, this method determines the absolute interface-state density profiles on the drain and source sides of transistors, extends the available scanning range, and provides self-consistent testing procedures to estimate the error induced by device simulation and testing parameters. This technique has been used to study the hot carrier degradation of submicron LDD (lightly doped drain) devices. The results indicate that the hot carrier damage occurred inside the LDD region. This damaged location can be shifted by changing the tip dose of the LDD region to improve the hot carrier performance of transistors.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Accurate characterization of the gate-N/sup -/ overlapped LDD (lightly doped drain) is carried out, based on the newly extracted L/sub eff/ which corresponds to the metallurgical channel length. Current drive improvement of the overlapped LDD over the conventional LDD is not so large as expected when the comparison is based on the same metallurgical channel length. Gate-source/drain overlap capacitance calculated from the newly extracted overlap length is useful for accurate analysis of propagation delay. It is shown that the current drive improvement of the overlapped LDD does not overcome the increase of the overlap capacitance and that the propagation delay of the inverter with overlapped LDD is larger than that of the conventional LDD, when these two LDDs are optimized for hot carrier reliability. >

In this paper, Photon Emission Microscopy (PEM) and micro-Raman Spectroscopy (μRS) are applied for temperature profile measurements and failure characterization in gg-nMOS ESD protection devices. The measurements were carried out in avalanche and snapback biasing conditions. A correlation between the temperature profile obtained by μRS and the light emission location, measured by PEM, is observed for non-degraded devices. In addition, ESD-degraded devices were studied. PEM, μRS, Spectroscopic Photon Emission Microscopy (SPEM) and electrical measurements were used to investigate the origin of the light emitted at the failure site. They showed that the light emission occurring at the failure site is due to impact ionization.

A novel analytical method applying combined electron beam induced current (EBIC) imaging based on scanning electron microscopy (SEM) and focused ion beam (FIB) cross sectioning in a SEM/FIB dualbeam system is presented. The method is demonstrated in several case studies for process characterization and failure analysis of thin film technology based Solar cells, including Silicon (CSG), Cadmium Telluride (CdTe) and Copper Indium Selenide (CIS) absorbers. While existing techniques such as electro-, photoluminescence spectroscopy and lock-in thermography are able to locate the larger, electrically active defects reasonably fast on a large area, the FIB-SEM EBIC system is uniquely capable of detecting sub-micron, sub-surface defects and of analysing these defects in the same system. In combination with a FIB, the localized region of interest can be easily cross sectioned and additional EBIC analysis can be applied for a three dimensional analysis of the p/n junction.

We investigated the lifetimes for various poly-Si thin film transistor (TFT) structures. A gate-overlapped lightly doped drain (GOLDD) structure was self-aligned by the side etching of Al-Nd in an Al-Nd/Mo gate electrode. The dopant activation process in the LDD regions of GOLDD TFTs was performed by using a H/sub 2/ ion-doping technique. We also observed the effect of lifetime on the source/drain activation process. The thermal annealing of the source/drain region was found to extend the lifetime. The predicted lifetime of our GOLDD poly-Si TFT is superior to those of non-lightly doped drain (non-LDD) and lightly-doped drain (LDD) poly-Si TFTs. The trapped-electron density at the drain junction after bias-stressing was also investigated using a two-dimensional (2-D) simulation.

Substrate current characteristics of conventional minimum overlap, DDD (double-diffused drain), and LDD (lightly doped drain) n-channel MOSFETs with various LDD n/sup -/ doses have been studied. Threshold voltage shift, transconductance degradation, and change of substrate current for these devices after stressing were also investigated. The minimum gate/drain overlap devices had the highest substrate current and the worst hot-electron-induced degradation. The amount of gate-to-n/sup +/ drain overlap in LDD devices was an important factor for hot-electron effects, especially for devices with low LDD n/sup -/ doses. The injection of hot holes into gate oxide in these devices at small stressed gate voltages was observed and was clearly reflected in the change of substrate current. The device degradation of low-doped LDD n-channel MOSFETs induced by AC stress was rather severe.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Nonzero implantation tilt angles are shown to cause an asymmetry in high-field effects, such as bipolar snapback and hot carrier injection, even when adequate source/drain overlap is achieved. This effect can cause large variations in a MOSFET's reliability, depending on its orientation and location within the wafer. Based on two-dimensional process and device simulations, it is shown that the Lightly Doped Drain (LDD) is more promising than the Graded Source/Drain (GSD) in avoiding these asymmetrical high-field effects at submicron dimensions. Guidelines are presented for the design of an optimized LDD structure, and substrate current is proposed as the best monitor for asymmetries in source/drain profiles.

Optimization of the n/sup -/ region concentration for n-channel MOSFET's with a lightly doped drain (LDD) structure was investigated, based on an analysis of the substrate current characteristics. When a substrate current tailing is observed, which is peculiar to the LDDFET with a low-concentration n-region, a gate current is not observed, which suggests strong resistance against hot-carrier injection. This was confirmed by a bias stress test. The optimized surface concentration for the n/sup -/ region ranges from 1 x 10/sup18/ cm/sup -3/ to 2.5 X 10/sup 18/ cm/sup -3/ under negligible V/sub TH/ shift and less than 25-percent driving capability degradation, compared to values for a conventional MOSFET.

This article presents an integrated current mode configurable analog block (CAB) system for field-programmable analog array (FPAA). The proposed architecture is based on the complementary metal-oxide semiconductor (CMOS) transistor level design where MOSFET transistors operating in the saturation region are adopted. The proposed CAB architecture is designed to implement six of the widely used current mode operations in analog processing systems: addition, subtraction, integration, multiplication, division, and pass operation. The functionality of the proposed CAB is demonstrated through these six operations, where each operation is chosen based on the user’s selection in the CAB interface system. The architecture of the CAB system proposes an optimized way of designing and integrating only three functional cells with the interface circuitry to achieve the six operations. Furthermore, optimized programming and digital tuning circuitry are implemented in the architecture to control and interface with the functional cells. Moreover, these designed programming and tuning circuitries play an essential role in optimizing the performance of the proposed design. Simulation of the proposed CMOS Transistor Based CAB system is carried out using Tanner EDA Tools in 0.35 μm standard CMOS technology. The design uses a V power supply and results in maximum 3 dB bandwidth of 34.9 MHz and an approximate size of 0.0537 . This demonstrates the advantages of the design over the current state-of-the-art designs presented for comparison in this article. Consequently, the proposed design has a clear aspect of simplicity, low power consumption, and high bandwidth operation, which makes it a suitable candidate for mobile telecommunications applications.

A comparison of device degradation due to hot-electron injection is made for conventional MOSFET's and lightly doped drain (LDD) structures. The studies indicate that, for an optimized LDD structure, critical device parameters, such as threshold voltage, transconductance, and linear and saturated current drives, show significantly reduced degradation when subjected to accelerated life testing. These results imply long-term stability for LDD devices used in VLSI circuits.

Metal gate technology for nanoscale transistors—material selection and process integration issues