An Optimized and Reliable LDD Structure for 1-/spl mu/m NMOSFET Based on Substrate Current Analysis

Hot-carrier (HC) degradation phenomena in p-channel lightly doped drain (LDD) MOSFETs and the effects of an LDD structure in minimizing HC degradation are described. Hot-electron injection in p-channel LDD MOSFETs causes effective channel length shrinkage. This phenomenon is also observed in conventional p/sup +/-drain MOSFETs but differs greatly from that in n-channel LDD MOSFETs. This is because hot electrons trapped in gate SiO/sub 2/ accumulate carriers (holes) along the channel region near the drain and decrease the pinchoff region. On the other hand, the LDD region in p-channel MOSFETs reduces HC generation to one-tenth of that in p/sup +/-drain MOSFETs under the same applied voltage. Moreover, the lifetimes of the LDD MOSFETs defined as how long it takes the transconductance deviation to reach 10% are longer by two orders of magnitude than those of the p/sup +/-drain MOSFETs under the same HC generation conditions. To obtain the best lifetime, it is shown that the optimum boron dose in the LDD region is between 1 and 3*10/sup 13/ cm/sup -2/. >

Substrate current characteristics of conventional minimum overlap, DDD (double-diffused drain), and LDD (lightly doped drain) n-channel MOSFETs with various LDD n/sup -/ doses have been studied. Threshold voltage shift, transconductance degradation, and change of substrate current for these devices after stressing were also investigated. The minimum gate/drain overlap devices had the highest substrate current and the worst hot-electron-induced degradation. The amount of gate-to-n/sup +/ drain overlap in LDD devices was an important factor for hot-electron effects, especially for devices with low LDD n/sup -/ doses. The injection of hot holes into gate oxide in these devices at small stressed gate voltages was observed and was clearly reflected in the change of substrate current. The device degradation of low-doped LDD n-channel MOSFETs induced by AC stress was rather severe.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Gate current and substrate current characteristics of submicron NMOSFET with asymmetrical lightly doped drain (LDD) structures are studied. It is newly found that the gate current also has a double-hump phenomenon, as does the substrate current. This new phenomenon can be estimated from impact ionization and the hot-electron emission mechanism. Furthermore, it is newly clarified that the threshold voltage shift after DC stress can be well explained by the gate current over the whole range of stress conditions.

Accurate characterization of the gate-N/sup -/ overlapped LDD (lightly doped drain) is carried out, based on the newly extracted L/sub eff/ which corresponds to the metallurgical channel length. Current drive improvement of the overlapped LDD over the conventional LDD is not so large as expected when the comparison is based on the same metallurgical channel length. Gate-source/drain overlap capacitance calculated from the newly extracted overlap length is useful for accurate analysis of propagation delay. It is shown that the current drive improvement of the overlapped LDD does not overcome the increase of the overlap capacitance and that the propagation delay of the inverter with overlapped LDD is larger than that of the conventional LDD, when these two LDDs are optimized for hot carrier reliability. >

A guideline for n/sup /spl minus// fully gate overlapped (FOLD) structure design optimization has been studied. From the viewpoint of reliability, the greatest reduction in substrate current directly leads to the most reliable n/sup /spl minus// design for the FOLD structure. The current path modulation phenomenon due to the trapped charge at the n/sup /spl minus// extension region dominates the hot-carrier induced characteristics change for conventional lightly doped drain (LDD) structure with side-wall spacer. This phenomenon is minimized in the FOLD structure due to its higher controllability of the gate electrode than the LDD structure at the n/sup /spl minus// extension region. Furthermore, it was also confirmed that the 0.3 /spl mu/m optimized FOLD structure can achieve high circuit performance at 3.3 V operation, maintaining hot-carrier resistance. >

A novel method of determining the spatial distribution of interface states of MOS transistors by charge pumping measurement has been developed. Unlike other existing methods, this method determines the absolute interface-state density profiles on the drain and source sides of transistors, extends the available scanning range, and provides self-consistent testing procedures to estimate the error induced by device simulation and testing parameters. This technique has been used to study the hot carrier degradation of submicron LDD (lightly doped drain) devices. The results indicate that the hot carrier damage occurred inside the LDD region. This damaged location can be shifted by changing the tip dose of the LDD region to improve the hot carrier performance of transistors.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An asymmetrical LDD structure next to the gate was used to improve the breakdown voltages and short-channel characteristics (such as subthreshold currents, threshold voltage uniformity, and output conductance) of self-aligned gate heterostructure FETs (HFETs). This approach decreases impact ionization and increases the breakdown voltage. Previous approaches have created symmetrical lightly doped regions around the gate by using a sidewall spacer, which resulted in high source resistances and transconductance degradation, leading to a tradeoff in transconductance and breakdown voltage. In the LDD HFET, drain-to-source breakdown voltage increased from 4.5 to 12 V and drain-to-gate breakdown voltage improved from 8.8 to 25 V, while the transconductance remained unchanged at 250 mS/mm, as the length of the lightly doped region is varied from 0 to 1 mu m. Experimental data show that the LDD structure eliminates threshold voltage roll off and improves V/sub T/ uniformity across a 3-in. wafer at gate lengths of 0.55 mu m. Further analysis of the subthreshold characteristics and the threshold voltage sensitivity to drain bias shows that the LDD HFET is much less sensitive to drain bias than the conventional HFET.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A comparison of device degradation due to hot-electron injection is made for conventional MOSFET's and lightly doped drain (LDD) structures. The studies indicate that, for an optimized LDD structure, critical device parameters, such as threshold voltage, transconductance, and linear and saturated current drives, show significantly reduced degradation when subjected to accelerated life testing. These results imply long-term stability for LDD devices used in VLSI circuits.

We present a simple method to extract the effective doping concentration related to the LDD (Lightly Doped Drain) regions in fully depleted SOI MOSFETs. The series resistance of an LDD structure MOSFET is composed of different components, the LDD series resistance, being the dominant one. The proposed method uses the back gate voltage influence on the back interface below the LDD region. MEDICI simulations were used to support the analysis.

Nonzero implantation tilt angles are shown to cause an asymmetry in high-field effects, such as bipolar snapback and hot carrier injection, even when adequate source/drain overlap is achieved. This effect can cause large variations in a MOSFET's reliability, depending on its orientation and location within the wafer. Based on two-dimensional process and device simulations, it is shown that the Lightly Doped Drain (LDD) is more promising than the Graded Source/Drain (GSD) in avoiding these asymmetrical high-field effects at submicron dimensions. Guidelines are presented for the design of an optimized LDD structure, and substrate current is proposed as the best monitor for asymmetries in source/drain profiles.

In this paper, a simple method to optimize the reliability concerns in the input/output (I/O) circuits is proposed and verified. Moreover, less masking steps in the process can be achieved. In the process, super steep retrograde channel is only implemented at core transistors to have good gate oxide integrity in the I/O regions. A modified lightly doped drain (LDD) structure formed by arsenic with phosphorus co-implant before poly re-oxidation is used to have long hot carrier lifetime. With the novel protection structure, the I/O circuits can achieve high electro-static discharge (ESD) failure threshold.

A new and simplistic approach is proposed to model the device conductances of submicrometer Lightly Doped Drain (LDD) MOSFETs. We model the LDD MOSFET as a conventional MOSFET with, a series resistance. The series resistance in the channel region is accounted as a voltage drop at the drain end by replacing the drain to source voltage with an effective drain to source voltage V/sub deff/. This method is much simpler and less time consuming in comparison with many other modeling approaches in which the lengthy procedure of calculating the series resistance and electric field is involved. New closed form expressions for the transconductance and the drain conductance are derived. The channel resistance is also evaluated from the drain conductance. A comparative study of the transconductance, drain conductance and channel resistance of LDD and conventional MOSFETs is carried out. The results show a lower current driving capability of the drain engineered MOS devices over the conventional ones.

The authors have proposed a novel structure which satisfies both high performance and high reliability with re-oxidized nitrided oxide (RNO) film in the sidewall of the LDD (lightly doped drain) transistor using rapid thermal nitridation (RTN). With this structure, the hot-carrier resistance of the LDD can be improved without the degradation of mobility as seen in MOSFETs having the RNO film as a gate insulator. Hot-carrier resistance against drain avalanche hot carrier injection is improved without degrading the resistance against channel-hot-electron injection or the mobility. Moreover, the authors have studied the nature of the RNO films in contrast to oxide films from the viewpoint of hot-carrier resistance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

It is shown that in 0.15-/spl mu/m NMOSFETs the device lifetime under channel hot-carrier (CHC) stress is lower than that under drain avalanche hot-carrier (DAHC) stress and therefore the hot-carrier stress-induced device degradation in 0.15-/spl mu/m NMOSFETs cannot be explained in the framework of the lucky electron model (LEM). Our investigation suggests that such a "non-LEM effect" may be due to increased interface state generation by the movement of the maximum impact ionization site from the lightly doped drain (LDD) diffusion region to the boundary of the bulk and LDD region beneath the gate oxide. This paper provides experimental evidence for the non-LEM effect by comparing the degradation characteristics and the maximum impact ionization sites as a function of gate oxide thickness and gate length.

Extraction of the lightly doped drain concentration of fully depleted SOI NMOSFETs using the back gate bias effect