Reduced hot-electron effects in MOSFET's with an optimized LDD Structure

Substrate current characteristics of conventional minimum overlap, DDD (double-diffused drain), and LDD (lightly doped drain) n-channel MOSFETs with various LDD n/sup -/ doses have been studied. Threshold voltage shift, transconductance degradation, and change of substrate current for these devices after stressing were also investigated. The minimum gate/drain overlap devices had the highest substrate current and the worst hot-electron-induced degradation. The amount of gate-to-n/sup +/ drain overlap in LDD devices was an important factor for hot-electron effects, especially for devices with low LDD n/sup -/ doses. The injection of hot holes into gate oxide in these devices at small stressed gate voltages was observed and was clearly reflected in the change of substrate current. The device degradation of low-doped LDD n-channel MOSFETs induced by AC stress was rather severe.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Hot-carrier (HC) degradation phenomena in p-channel lightly doped drain (LDD) MOSFETs and the effects of an LDD structure in minimizing HC degradation are described. Hot-electron injection in p-channel LDD MOSFETs causes effective channel length shrinkage. This phenomenon is also observed in conventional p/sup +/-drain MOSFETs but differs greatly from that in n-channel LDD MOSFETs. This is because hot electrons trapped in gate SiO/sub 2/ accumulate carriers (holes) along the channel region near the drain and decrease the pinchoff region. On the other hand, the LDD region in p-channel MOSFETs reduces HC generation to one-tenth of that in p/sup +/-drain MOSFETs under the same applied voltage. Moreover, the lifetimes of the LDD MOSFETs defined as how long it takes the transconductance deviation to reach 10% are longer by two orders of magnitude than those of the p/sup +/-drain MOSFETs under the same HC generation conditions. To obtain the best lifetime, it is shown that the optimum boron dose in the LDD region is between 1 and 3*10/sup 13/ cm/sup -2/. >

An asymmetrical LDD structure next to the gate was used to improve the breakdown voltages and short-channel characteristics (such as subthreshold currents, threshold voltage uniformity, and output conductance) of self-aligned gate heterostructure FETs (HFETs). This approach decreases impact ionization and increases the breakdown voltage. Previous approaches have created symmetrical lightly doped regions around the gate by using a sidewall spacer, which resulted in high source resistances and transconductance degradation, leading to a tradeoff in transconductance and breakdown voltage. In the LDD HFET, drain-to-source breakdown voltage increased from 4.5 to 12 V and drain-to-gate breakdown voltage improved from 8.8 to 25 V, while the transconductance remained unchanged at 250 mS/mm, as the length of the lightly doped region is varied from 0 to 1 mu m. Experimental data show that the LDD structure eliminates threshold voltage roll off and improves V/sub T/ uniformity across a 3-in. wafer at gate lengths of 0.55 mu m. Further analysis of the subthreshold characteristics and the threshold voltage sensitivity to drain bias shows that the LDD HFET is much less sensitive to drain bias than the conventional HFET.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Accurate characterization of the gate-N/sup -/ overlapped LDD (lightly doped drain) is carried out, based on the newly extracted L/sub eff/ which corresponds to the metallurgical channel length. Current drive improvement of the overlapped LDD over the conventional LDD is not so large as expected when the comparison is based on the same metallurgical channel length. Gate-source/drain overlap capacitance calculated from the newly extracted overlap length is useful for accurate analysis of propagation delay. It is shown that the current drive improvement of the overlapped LDD does not overcome the increase of the overlap capacitance and that the propagation delay of the inverter with overlapped LDD is larger than that of the conventional LDD, when these two LDDs are optimized for hot carrier reliability. >

We present a simple method to extract the effective doping concentration related to the LDD (Lightly Doped Drain) regions in fully depleted SOI MOSFETs. The series resistance of an LDD structure MOSFET is composed of different components, the LDD series resistance, being the dominant one. The proposed method uses the back gate voltage influence on the back interface below the LDD region. MEDICI simulations were used to support the analysis.

Medium-voltage lateral structures for power NMOS devices, suitable for integration with standard low-voltage CMOS control circuits in power ICs, are presented. Two device types were fabricated on 1.5- mu m micron, N-well, two-metal-layer, 10-mask CMOS standard technology. Design rules and device mask geometry were adapted for enlarging the operating voltage range beyond 5 V. The LDD (lightly doped drain) NMOS transistor is based on the LDD concept. The LDSD (light doped source drain) NMOS transistor applies the same concept to both source and drain terminals. On-resistance as low as 9 m Omega cm/sup 2/ and breakdown voltages of 20 V were experimentally obtained. Monolithic integration of multiple switches with low-voltage control is possible, since structures are electrically compatible. The electric characterization and proposed model for LDD and LDSD NMOS devices in commutation are presented. These structures are aimed at smart power ICs using standard CMOS technologies, for low power applications. Experimental results are presented. >

A novel method of determining the spatial distribution of interface states of MOS transistors by charge pumping measurement has been developed. Unlike other existing methods, this method determines the absolute interface-state density profiles on the drain and source sides of transistors, extends the available scanning range, and provides self-consistent testing procedures to estimate the error induced by device simulation and testing parameters. This technique has been used to study the hot carrier degradation of submicron LDD (lightly doped drain) devices. The results indicate that the hot carrier damage occurred inside the LDD region. This damaged location can be shifted by changing the tip dose of the LDD region to improve the hot carrier performance of transistors.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An extraction method for an effective channel length (L/sub eff/) on lightly doped drain (LDD) MOSFETs is proposed. In the method, the L/sub eff/ is obtained by the linear extrapolation of the gate-bias-dependent L/sub eff/ to the threshold voltage. In order to clear the difference of the gate bias dependence of the L/sub eff/ among various LDD structures, the LDDs are examined with experiments and simulations. The L/sub eff/ of LDDs corresponds to the metallurgical length. It is shown that MOSFET parameters can be reasonably characterized when the L/sub eff/ obtained by the method is used.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A new type of field effect transistor (FET), the double doping polysilicon gate (DDPG) Lightly-doped-drain (LDD) MOSFET, is proposed and demonstrated. The gate of the DDPG LDD MOSFET adopts gate engineering. This novel gate structure takes advantage of material work function. The arrangement is such that the gate near the source is comprised of P-type polysilicon and the gate near the drain is N-type polysilicon. The model is simulated with a 2-D device simulator MEDICI over wide range of device parameters and bias conditions and we get curves such as electric field, surface potential, threshold voltage and driving current. The simulation result shows that an appropriate threshold voltage can be gotten by changing the doping concentration of polysilicon. Meanwhile, the driving capacity is greatly improved compared with the conventional MOSFET. The process of the structure is not complicated which can be easily achieved today.

A new and simplistic approach is proposed to model the device conductances of submicrometer Lightly Doped Drain (LDD) MOSFETs. We model the LDD MOSFET as a conventional MOSFET with, a series resistance. The series resistance in the channel region is accounted as a voltage drop at the drain end by replacing the drain to source voltage with an effective drain to source voltage V/sub deff/. This method is much simpler and less time consuming in comparison with many other modeling approaches in which the lengthy procedure of calculating the series resistance and electric field is involved. New closed form expressions for the transconductance and the drain conductance are derived. The channel resistance is also evaluated from the drain conductance. A comparative study of the transconductance, drain conductance and channel resistance of LDD and conventional MOSFETs is carried out. The results show a lower current driving capability of the drain engineered MOS devices over the conventional ones.

AlGaN/GaN high electron mobility transistors (HEMTs) with lightly doped drain (LDD) structures were fabricated using an Si ion implantation technique. The HEMTs show an obvious merit of enhancement of on-state breakdown voltage (Vbr) of as high as 180 V, where that of a reference device without the LDD structure was 130 V. We also confirmed that resistance values at heavily doped drain regions were not changed by the introduction of the LDD structure.

In this paper, a universal and computationally efficient subthreshold model for sub-100-nm nonuniformly doped channel MOSFET has been presented. The model incorporates drain-induced barrier lowering effect by means of the short-channel depletion width parameter d, which is evaluated using the voltage doping transformation method. The model can accurately predict the following: 1) surface potential; 2) electric field; 3) threshold voltage; and 4) subthreshold slope, for various lateral as well as transverse channel-engineered structures such as retrograde, graded channel, lightly doped drain (LDD), halo, and pocket implant technology for sub-100-nm channel length. In this paper, we have also proposed a novel device architecture incorporating the benefits of asymmetric halo and LDD doping. The analytical results have been verified by ATLAS 2-D device simulation software.

A guideline for n/sup /spl minus// fully gate overlapped (FOLD) structure design optimization has been studied. From the viewpoint of reliability, the greatest reduction in substrate current directly leads to the most reliable n/sup /spl minus// design for the FOLD structure. The current path modulation phenomenon due to the trapped charge at the n/sup /spl minus// extension region dominates the hot-carrier induced characteristics change for conventional lightly doped drain (LDD) structure with side-wall spacer. This phenomenon is minimized in the FOLD structure due to its higher controllability of the gate electrode than the LDD structure at the n/sup /spl minus// extension region. Furthermore, it was also confirmed that the 0.3 /spl mu/m optimized FOLD structure can achieve high circuit performance at 3.3 V operation, maintaining hot-carrier resistance. >

A lightly doped drain (LDD) region, particularly a gate-overlapped LDD (GOLD) region, is subjected to a gate electric field and its gate-controlled resistance affects the device characteristics. We developed a new extraction method for determining the intrinsic characteristics of LDD MOSFETs using a simple series resistance model, in which the GOLD region is assumed to be a depletion MOSFET with a negative threshold voltage derived from C–V measurement. Polycrystalline-silicon (poly-Si) TFTs with a channel length of 4–100 µm were used for the test LDD samples, particularly GOLD MOSFETs. It was demonstrated that the new proposed method precisely extracts the intrinsic characteristics of poly-Si GOLD TFTs by comparing them with the intrinsic characteristics of poly-Si Self-Aligned (SA) TFTs extracted by the conventional method.

Extraction of the lightly doped drain concentration of fully depleted SOI NMOSFETs using the back gate bias effect