Drain structure optimization for highly reliable deep submicrometer n-channel MOSFET

An asymmetrical LDD structure next to the gate was used to improve the breakdown voltages and short-channel characteristics (such as subthreshold currents, threshold voltage uniformity, and output conductance) of self-aligned gate heterostructure FETs (HFETs). This approach decreases impact ionization and increases the breakdown voltage. Previous approaches have created symmetrical lightly doped regions around the gate by using a sidewall spacer, which resulted in high source resistances and transconductance degradation, leading to a tradeoff in transconductance and breakdown voltage. In the LDD HFET, drain-to-source breakdown voltage increased from 4.5 to 12 V and drain-to-gate breakdown voltage improved from 8.8 to 25 V, while the transconductance remained unchanged at 250 mS/mm, as the length of the lightly doped region is varied from 0 to 1 mu m. Experimental data show that the LDD structure eliminates threshold voltage roll off and improves V/sub T/ uniformity across a 3-in. wafer at gate lengths of 0.55 mu m. Further analysis of the subthreshold characteristics and the threshold voltage sensitivity to drain bias shows that the LDD HFET is much less sensitive to drain bias than the conventional HFET.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Hot-carrier (HC) degradation phenomena in p-channel lightly doped drain (LDD) MOSFETs and the effects of an LDD structure in minimizing HC degradation are described. Hot-electron injection in p-channel LDD MOSFETs causes effective channel length shrinkage. This phenomenon is also observed in conventional p/sup +/-drain MOSFETs but differs greatly from that in n-channel LDD MOSFETs. This is because hot electrons trapped in gate SiO/sub 2/ accumulate carriers (holes) along the channel region near the drain and decrease the pinchoff region. On the other hand, the LDD region in p-channel MOSFETs reduces HC generation to one-tenth of that in p/sup +/-drain MOSFETs under the same applied voltage. Moreover, the lifetimes of the LDD MOSFETs defined as how long it takes the transconductance deviation to reach 10% are longer by two orders of magnitude than those of the p/sup +/-drain MOSFETs under the same HC generation conditions. To obtain the best lifetime, it is shown that the optimum boron dose in the LDD region is between 1 and 3*10/sup 13/ cm/sup -2/. >

A salicide process for thin SIMOX MOSFETs was developed, and the prospect of device application in the submicron regime was examined by evaluating the current drivability of MOSFETs and analyzing its limiting factors in both short and long channel regions. One problem in the scaling of thin-SOI MOSFETs (especially for NMOS) was the lowered drain breakdown voltage caused by parasitic bipolar operation due to a floating body structure. Latch-up phenomena in a unit NMOS diminishes the reliable operation of the CMOS circuit. The problem can be solved by lowering the drain electric field to reduce generated holes from impact ionization which reinforces parasitic bipolar operation. The authors studied the LDD (lightly doped drain) structure and an advanced gate overlapped LDD structure for device application of the thin-SOI/MOSFET under and beyond the half-micron regime. >

We investigated the lifetimes for various poly-Si thin film transistor (TFT) structures. A gate-overlapped lightly doped drain (GOLDD) structure was self-aligned by the side etching of Al-Nd in an Al-Nd/Mo gate electrode. The dopant activation process in the LDD regions of GOLDD TFTs was performed by using a H/sub 2/ ion-doping technique. We also observed the effect of lifetime on the source/drain activation process. The thermal annealing of the source/drain region was found to extend the lifetime. The predicted lifetime of our GOLDD poly-Si TFT is superior to those of non-lightly doped drain (non-LDD) and lightly-doped drain (LDD) poly-Si TFTs. The trapped-electron density at the drain junction after bias-stressing was also investigated using a two-dimensional (2-D) simulation.

As the supply voltage is reduced, the speed superiority of BiCMOS over CMOS may be diminished, but BiCMOS still has the advantage of inducing relatively smaller characteristic degradation in nMOS transistors by suppressing the drain voltage in the gate. Introducing a new quantitative methodology to evaluate hot electron-induced degradation of nMOS transistor characteristics, this report finds that both BiNMOS gates and CBiMOS gates will have a considerable superiority over CMOS gates in the voltage range from 2.5 V to 3.3 V, even with the same nMOS transistor characteristics. BiNMOS is 30% faster than CMOS owing to amplification of the pMOS drain current by an npn transistor. CBiCMOS is 40% faster and has a sevenfold longer life than CMOS. The speed improvement comes from amplification of both pMOS and nMOS drain currents by npn and pnp transistors, respectively, and the lifetime improvement is due to the effect of the voltage drop through the pnp transistors on the drain terminal of the nMOS transistors. The analytical methodology was also utilized to choose an optimum drain structure, although CMOS necessitates the LDD (lightly doped drain), SD (single drain) structure. Thus, the speed of the gates can be further improved, and the speed of CBiCMOS is expected to be 45% faster than that of CMOS gates. Even in the case of SD structure, the lifetime of CBiCMOS was estimated to be two orders of magnitude longer than that of CMOS with LDD structure. © 1998 Scripta Technica. Electr Eng Jpn, 121(4): 56–64, 1997

AlGaN/GaN high electron mobility transistors (HEMTs) with lightly doped drain (LDD) structures were fabricated using an Si ion implantation technique. The HEMTs show an obvious merit of enhancement of on-state breakdown voltage (Vbr) of as high as 180 V, where that of a reference device without the LDD structure was 130 V. We also confirmed that resistance values at heavily doped drain regions were not changed by the introduction of the LDD structure.

We present a simple method to extract the effective doping concentration related to the LDD (Lightly Doped Drain) regions in fully depleted SOI MOSFETs. The series resistance of an LDD structure MOSFET is composed of different components, the LDD series resistance, being the dominant one. The proposed method uses the back gate voltage influence on the back interface below the LDD region. MEDICI simulations were used to support the analysis.

Optimization of the n/sup -/ region concentration for n-channel MOSFET's with a lightly doped drain (LDD) structure was investigated, based on an analysis of the substrate current characteristics. When a substrate current tailing is observed, which is peculiar to the LDDFET with a low-concentration n-region, a gate current is not observed, which suggests strong resistance against hot-carrier injection. This was confirmed by a bias stress test. The optimized surface concentration for the n/sup -/ region ranges from 1 x 10/sup18/ cm/sup -3/ to 2.5 X 10/sup 18/ cm/sup -3/ under negligible V/sub TH/ shift and less than 25-percent driving capability degradation, compared to values for a conventional MOSFET.

A substitutional self-aligned gate MESFET process for the half-micrometer gate GaAs IC that employs techniques of sidewall formation and precise pattern reversal using ECR (electron cyclotron resonance) CVD (chemical vapor deposition) is discussed. A FET with 0.45- mu m gate length showed high performance characteristics, such as a maximum transconductance of 440 mS/mm and a cutoff frequency of 39 GHz. This process has two advantages over conventional substitutional and refractory gate processes. First, it can incorporate an LDD (lightly doped drain) structure. Second, since the photoresist dummy gates are precisely reversed without using reactive ion etching (RIE) at all, the gate length is dependent only on lithography. The process was demonstrated by the preliminary fabrication of a 16 b*16 b multiplier with 50% yield. The process, with high-performance device characteristics, should fine broad applications in both half-micrometer gate level LSIs and analog ICs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The authors have proposed a novel structure which satisfies both high performance and high reliability with re-oxidized nitrided oxide (RNO) film in the sidewall of the LDD (lightly doped drain) transistor using rapid thermal nitridation (RTN). With this structure, the hot-carrier resistance of the LDD can be improved without the degradation of mobility as seen in MOSFETs having the RNO film as a gate insulator. Hot-carrier resistance against drain avalanche hot carrier injection is improved without degrading the resistance against channel-hot-electron injection or the mobility. Moreover, the authors have studied the nature of the RNO films in contrast to oxide films from the viewpoint of hot-carrier resistance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A comparison of device degradation due to hot-electron injection is made for conventional MOSFET's and lightly doped drain (LDD) structures. The studies indicate that, for an optimized LDD structure, critical device parameters, such as threshold voltage, transconductance, and linear and saturated current drives, show significantly reduced degradation when subjected to accelerated life testing. These results imply long-term stability for LDD devices used in VLSI circuits.

To realize high-resolution pixels in the CMOS image sensor, it is necessary to reduce low-frequency noise, particularly random telegraph signal (RTS) noise of the source-follower transistor (SFT). To achieve less relative variation of drain noise current, ΔID/ID, a metal–oxide–semiconductor field-effect transistor structure without the lightly doped drain (LDD) for the SFT transistor is proposed. Then, a comparison of RTS noise characteristics between the proposed SFT structure without LDD and the conventional SFT structure with LDD was conducted. Although the RTS noise occurrence probability of the proposed SFT structure without LDD is somewhat greater than that of the conventional SFT structure with LDD, the amplitude of relative variation of drain noise current of the proposed SFT structure is significantly less than that of the conventional SFT. Despite changes in several factors in the proposed SFT, such as effective channel length, trap depth profile in gate oxide, and random dopant fluctuation (RDF), it is believed that the change of trap depth profile is a primary factor for the improved RTS characteristic. Therefore, the proposed SFT is highly desirable for the high-resolution CMOS image sensor.

Extraction of the lightly doped drain concentration of fully depleted SOI NMOSFETs using the back gate bias effect

We propose novel ultrasmall metal-oxide-semiconductor (MOS) transistors with double-potential barriers. The structure is similar to the lightly doped drain (LDD) MOS transistors with upper and lower gates. The double-potential barriers, which are controlled by the upper gate voltage, are formed under the side wall spacers. It is confirmed by simulation that the tunneling current through the double-potential barriers is larger than the thermally excited current at 77 K. Then, the Coulomb blockade effects, i.e., the suppression of the tunneling current in the vicinity of the zero drain voltage and the Coulomb oscillation, are observable at 77 K.

Charge buildup damage to gate oxide during lightly doped drain (LDD) spacer oxide etch was studied by measuring gate leakage of fully processed transistors over thin oxide attached to area-intensive or edge-intensive polycide antenna structures over thick oxide. Wafers were etched at the LDD spacer oxide etch step for various overetch times ranging from −7% to +35%. It was found that gate oxide damage from charge buildup depended strongly on spacer overetch time. No charge buildup was detected before endpoint (defined as the time required to completely remove oxide from flat silicon surfaces—the polycide has a cap oxide layer on it, so the gate electrode is not exposed at endpoint), but significant charge buildup occurred through the polycide surface when etching was continued past endpoint. Gate leakage failures for transistors attached to large area-intensive antennas increased monotonically with overetch time, leading to 100% failure after 20%–30% overetch. This charge buildup damage began to occur even before the cap oxide was completely removed and the gate electrode was exposed to the plasma, suggesting that either the tetraethylorthosilicate oxide itself was not perfectly insulating or it became leaky after exposure to this high-energy oxide etch plasma with a dc bias of about −600 V.