Next Generation Error Correcting Capabilities Final Report CRADA No. TSB-952-94

Error control coding improves reliability and efficiency of wireless communication systems. This research delves into the latest advancements in error control coding schemes for wireless communication systems, with a specific focus on their application within the domain of Low Power Wide Area Networks (LPWANs) such as Narrowband Internet of Things (NB-IoT) systems, LoRa energy-efficient hardware design, random access control systems, and wireless sensor networks. In the context of LPWANs, particularly NB-IoT systems, we investigate the adaptive coding and modulation (ACM) in NB-IoT systems, which adapts coding rates and modulation techniques to changing channel circumstances. Comprehensive analysis of the literature review shows that the proposed approaches are more energy efficient and less error-prone than fixed coding and modulation schemes. Using Cell Design Methodology (CDM), Single Error Correction (SEC) codes are optimized for energy efficiency. Power and energy efficiency have improved in standard CMOS and CDM logic systems. This impacts IoT devices, memory storage, and security systems. Next, Forward Error Correction (FEC) is examined for ALOHA-based random-access control systems wherein packet loss rate and spectral efficiency metrics are mathematically calculated. FEC is beneficial, especially when time and frequency synchronization diverge. Monte Carlo simulations studied in the literature shows that FEC improves satellite communication systems. This review establishes benefits of FEC, notably in satellite communications systems. In addition, Wireless Sensor Networks (WSNs) error control techniques and network reliability and performance are examined along with Convolutional, Turbo, Low density parity check codes(LDPC), and Polar error correction coding (ECC) methods. We learn about their benefits, drawbacks, and implementation challenges by assessing their efficacy, efficiency, and applicability in wireless sensor networks (WSN) applications. This study further highlights advancements of energy-efficient error control coding when, integrated into network designs alongwith the trade-offs between efficacy and intricacy to help improve wireless communication networks. Finally, this study summarizes current error control coding approaches for wireless communication systems. We provide insights into improving reliability, energy conservation, and efficacy by examining ACM, CDM, FEC, and error correction coding (ECC) across varied domains including LPWAN and IoT technologies with earnest hope to facilitate researchers, engineers, and professionals working in the field of error control coding in wireless communication.

Error correction codes (ECCs) are commonly used in computer systems to protect information from errors. For example, single error correction (SEC) codes are frequently used for memory protection. Due to continuous technology scaling, soft errors on registers have become a major concern, and ECCs are required to protect them. Nevertheless, using an ECC increases delay, area and power consumption. In this way, ECCs are traditionally designed focusing on minimizing the number of redundant bits added. This is important in memories, as these bits are added to each word in the whole memory. However, this fact is less important in registers, where minimizing the encoding and decoding delay can be more interesting. This paper proposes a method to develop codes with 1-gate delay encoders and 4-gate delay decoders, independently of the word length. These codes have been designed to correct single errors only in data bits to reduce the overhead.

Error-correcting codes (ECC) are widely used during data transfer in wireless communication systems as well as in computer memory architectures. The error-correcting process is based on sending data with extra parity bits and decoding the received data for error correction. The first error detection and correction code, introduced in 1950, Hamming Code (7,4) is a linear error-correcting code able to detect and correct a single-bit error by encoding 7-bit data from 4-bit data, including 3 parity bits. Previous efforts using unipolar resistive random access memory (ReRAM) based in-memory computation of Hamming Code (7,4) resulted in 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> times lower power consumption compared to GPU and 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> times less than CPU-based computations. However further reduction of power consumption can be achieved by vector-matrix multiplication (VMM) using bipolar ReRAM arrays. In the VMM based approach, an encoding or decoding code matrix is stored in the array where it leverages the nonvolatile properties of ReRAM. With the VMM approach, the total number of computation cycles is not limited by the endurance of the ReRAM devices. Here we report the first experimental results of encoding and decoding Hamming code (7,4) using 1 transistor 1 hafnium oxide-based ReRAM (1T1R) arrays fabricated using 65nm CMOS technology. Our results show bipolar 1T1R arrays can correctly encode 4-bit message data to 7 bit encoded data as well as error position detection with overall 3 fold less power consumption than previously reported unipolar ReRAM crossbar array-based computation. Furthermore, we propose and simulate a peripheral circuit to convert the analog column output from a 1T1R array to single-bit binary output using the Cadence Spectre simulator. Our results pave the way for using a memristor-based fast and scalable hardware solution for encoding decoding of error-correcting codes

Soft errors caused by radiation particles are becoming an increasingly important issue for memory reliability. Traditionally, Single Error Correction (SEC) codes have been used to correct soft errors. Such codes can correct one error per memory word, but as errors become more frequent they may be insufficient. More complex error correction codes (ECCs) could be used, but they typically require complex decoders which impact memory area and speed. In this paper, the use of Euclidean geometry (EG) Codes for memory applications is studied. The results show that these codes, which provide powerful error correction capabilities, can be implemented efficiently in terms of area and latency.

Guessing Random Additive Noise Decoding (GRAND) is a recently proposed Maximum Likelihood (ML) decoding technique. Irrespective of the structure of the error correcting code, GRAND tries to guess the noise that corrupted the codeword in order to decode any linear error-correcting block code. GRAND Markov Order (GRAND-MO) is a variant of GRAND that is useful to decode error correcting code transmitted over communication channels with memory which are vulnerable to burst noise. Usually, interleavers and de-interleavers are used in communication systems to mitigate the effects of channel memory. Interleaving and de-interleaving introduce undesirable latency, which increases with channel memory. To prevent this added latency penalty, GRAND-MO can be directly used on the hard demodulated channel signals. This work reports the first GRAND-MO hardware architecture which achieves an average throughput of up to $52$ Gbps and $64$ Gbps for a code length of $128$ and $79$ respectively. Compared to the GRANDAB, hard-input variant of GRAND, the proposed architecture achieves $3$ dB gain in decoding performance for a target FER of $10^{-5}$. Similarly, comparing the GRAND-MO decoder with a decoder tailored for a $(79,64)$ BCH code showed that the proposed architecture achieves 33$\%$ higher worst case throughput and $2$ dB gain in decoding performance.

One of the tasks of system identification within the modern signal processing system is the task of identification of unknown error-correction code (ECC). System identification can be done using various methods. Anyway, the more knowledge one has about the possible system structure provides better solution for system identification. Here we take a look into digital communication systems uses ECC, which are the major part of modern communication systems are. We create a new practical approach for identification of a priori unknown ECC being used over the transmission channel of the communication system which is examined for identification purposes. The approach is based as Big Data application which can provide new source for the study. Shown that usage of new approach provides better speed for system identification making the process of identification faster, more reliable, with better quality for solution found and with lower requirements for quality of the transmission channel.

Non-volatile memories are paid attention to as a promising alternative to memory design. Data stored in them still may be destructed due to crosstalk and radiation. We can restore the data by using error-correcting codes which require extra bits to correct bit errors. Further, non-volatile memories consume ten to hundred times more energy than normal memories in bit-writing. When we configure them using error-correcting codes, it is quite necessary to reduce writing bits. In this paper, we propose a method to generate a bit-write-reducing code with error-correcting ability. We first pick up an error-correcting code which can correct t-bit errors. We cluster its codeswords and generate a cluster graph satisfying the S-bit flip conditions. We assign a data to be written to each cluster. In other words, we generate one-to-many mapping from each data to the codewords in the cluster. We prove that, if the cluster graph is a complete graph, every data in a memory cell can be re-written into another data by flipping at most S bits keeping error-correcting ability to t bits. We further propose an efficient method to cluster error-correcting codewords. Experimental results demonstrate that, when we apply our bit-write-reducing code to MediaBench applications, it can reduce writing-bit counts by up to 28.2% and also energy consumption of non-volatile memory cells by up to 27.9% compared to existing error-correcting codes keeping the same error-correcting ability. This paper proposes the world-first theoretically near-optimal bit-write-reducing code with error-correcting ability based on the efficient coding theories.

As the size of on-chip SRAM caches is increasing rapidly and the physical dimension of the SRAM devices is decreasing, reliability of caches is becoming a growing concern. This is because with increased size of caches, the likelihood of radiation-induced soft faults also increases. As a result, information redundancy in the form of Error Correcting Codes (ECC) is becoming extremely important, especially to protect the larger sized last level caches (LLCs). In typical ECCs, extra redundancy bits are added to every row to detect and correct errors. There is additional encoding (while writing data) and decoding (while reading data) procedures required as well. In caches, these additional area, power and latency overheads need to be minimized as much as possible. To address this problem, we present in this paper Parity++: a novel unequal message protection scheme for last level caches that preferentially provides stronger error protection to certain "special messages". This protection scheme provides Single Error Detection (SED) for all messages and Single Error Correction (SEC) for a subset of messages. Thus, it is stronger than just a basic SED parity and has much lower parity storage overhead (4X lower for a 64-bit memory) and lower error detection energy than a traditional Single Error Correcting, Double Error Detecting (SECDED) code. We also evaluate Parity++ with a memory speculation procedure that can be used with any ECC scheme to hide the decoding latency while reading messages when there are no errors.

In digital communication systems, error correction codes are used to recover data that has been disturbed in a noisy environment. Convolutional code is a commonly used error correction code. In non-cooperative communication systems, it is very meaningful to blindly identify the synchronization position and coding parameters of convolutional codes. Existing reference had proposed a blind recognition algorithm for coding parameters of k/n rate convolutional codes in a noisy environment, but it didn't take into account the case where the received code words were not synchronized. In this paper, this problem is improved by using the quasi-correlation between the receive sequence and the check matrix to estimate the synchronization position, while obtaining the check matrix. It implements blind recognition of the synchronization position and coding parameters of k/n rate convolutional codes in a noisy environment. Simulation experimental results show that the improved algorithm in this paper is effective.

With the rapid increase in the volume of transmitted information and the proliferation of distributed network infrastructures, the requirements for the security and reliability of communication channels are steadily intensifying. Traditional protection methods, such as virtual private networks (VPNs), are primarily aimed at ensuring confidentiality and authenticity through cryptographic algorithms, while typically lacking resilience to transmission-level errors arising from noise, interference, or hardware failures. In contrast, error correction codes—such as Hamming codes—are well-established tools for detecting and correcting random errors in physical channels, but they do not address intentional threats like interception, modification, or traffic analysis. This paper presents a hybrid cascading model for secure and reliable data transmission that integrates cryptographic encapsulation via VPN technologies with structural redundancy provided by error correction coding. A specific focus is placed on the use of Hamming codes extended by an additional parity bit applied at the post-encryption stage, enabling the protection of VPN packet integrity even under noisy channel conditions. The architecture of the proposed model is examined in detail, including its modular components, processing flow, and the various possible configurations of encoding and encryption blocks. Particular attention is given to analysing the threat surfaces present at each phase of transmission—prior to tunneling, during transport, and at the decryption stage—and assessing the system’s robustness through probabilistic reliability metrics and redundancy coefficients. Simulation-based modelling supports the theoretical framework and confirms that the combined use of encryption and redundancy coding significantly enhances overall communication resilience. The results underscore the importance of a comprehensive approach to secure data transmission that jointly addresses logical security threats and physical-level vulnerabilities.

Algebraic codes are important in communication and storage systems where soft information is limited and decoding efficiency is critical. Among them, algebraic-geometric (AG) codes are promising candidates to replace the widely used Reed-Solomon (RS) codes. However, their more sophisticated algebraic structure results in high decoding complexity, hindering their practical application. This paper proposes a novel interpolation-based algebraic soft decoding (ASD) for one of the most important AG codes - Hermitian codes. Given a designed maximum decoding output list size (OLS), the interpolation module is constructed, and the decoding is formulated as finding a desired Gröbner basis of this module that contains the interpolation polynomial. The re-encoding transform (ReT) specifically designed for ASD is proposed, enabling the modified basis reduction (BR) interpolation to achieve lower complexity. The ReT is formulated by defining Lagrange interpolation polynomials over the Hermitian function fields and appropriately choosing the re-encoding points. By exploiting the linear code property, the ReT transforms a subset of interpolation points to have zero <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">z</i>-coordinates, which allows a common factor to be extracted from the module basis polynomials, thereby simplifying the interpolation. This paper further proposes an improved ReT employing more re-encoding points. It enables the common factor to have a greater degree, yielding a more significant complexity reduction. This also leads to an early termination for the decoding. Theoretical analysis and numerical results demonstrate that the two proposed ReT schemes efficiently facilitate the ASD for Hermitian codes.

A traditional approach to solving the problem of local compaction of a horizontal microcode is described. In accordance with this approach any linear segment of the source microcode is made to correspond to a unique data dependence graph. A notion of the data exchange between the microoperations is introduced. Based on this notion, a model is developed that demonstrates that a given linear segment is, generally, associated with a set of semantically equivalent data dependence graphs, which differ from one another by the order of the execution of the exchanges on shared static resources. An optimization combinatorial problem on the permutation of the exchanges of a linear segment is formulated. Conditions for the existence of an admissible solution are studied, and a method for finding it is developed. A new space of solutions for the local compaction problem is obtained through the use of a new data dependence graph, which is, in a sense, better than the original one.

Emerging Memories (EMs) could benefit from Error Correcting Codes (ECCs) able to correct few errors in a few nanoseconds. The low latency is necessary to meet the DRAM-like and/or eXecuted-in-Place requirements of Storage Class Memory devices. In this paper we design an ECC decoder of a shortened BCH code with 256-data-bit page able to correct three errors in less than 3 ns. The tight latency constraint is met by precomputing the coefficients of carefully chosen Error Locator Polynomials, by optimizing the operations in the Galois Fields and by resorting to a fully parallel combinatorial implementation of the decoder. The latency and the area occupancy are first estimated based on the number of elementary gates.Eventually,the implementation of the solution by Synopsys topographical synthesis methodology in 54nm logic gate length CMOS technology gives a latency lower than 3ns and a total area less than250 · 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Error detection is a fundamental need in most computer networks and communication systems in order to combat the effect of noise. Error detection techniques have also been incorporated with lossless data compression algorithms for transmission across communication networks. In this paper, we propose to incorporate a novel error detection scheme into a Shannon optimal lossless data compression algorithm known as Generalized Luröth Series (GLS) coding. GLS-coding is a generalization of the popular Arithmetic Coding which is an integral part of the JPEG2000 standard for still image compression. GLS-coding encodes the input message as a symbolic sequence on an appropriate 1D chaotic map Generalized Luröth Series (GLS) and the compressed file is obtained as the initial value by iterating backwards on the map. However, in the presence of noise, even small errors in the compressed file leads to catastrophic decoding errors owing to sensitive dependence on initial values, the hallmark of deterministic chaos. In this paper, we first show that repetition codes, the oldest and the most basic error correction and detection codes in literature, actually lie on a Cantor set with a fractal dimension of }{} frac{1}{n} , which is also the rate of the code. Inspired by this, we incorporate error detection capability to GLS-coding by ensuring that the compressed file (initial value on the chaotic map) lies on a Cantor set. Even a 1-bit error in the initial value will throw it outside the Cantor set, which can be detected while decoding. The rate of the code can be adjusted by the fractal dimension of the Cantor set, thereby controlling the error detection performance.

The registers constraints are usually taken into account during the scheduling pass of an acyclic data dependence graph (DAG): any schedule of the instructions inside a basic block must bound the register requirement under a certain limit. In this work, we show how to handle the register pressure before the instruction scheduling of a DAG. We mathematically study an approach which consists in managing the exact upper-bound of the register need for all the valid schedules of a considered DAG, independently of the functional unit constraints. We call this computed limit the register saturation (RS) of the DAG. Its aim is to detect possible obsolete register constraints, i.e., when RS does not exceed the number of available registers. If it does, we add some serial edges to the original DAG such that the worst register need does not exceed the number of available registers. We propose an appropriate mathematical formalism for this problem. Our generic processor model takes into account superscalar, VLIW and EPIC/IA64 architectures. Our deeper analysis of the problem and our formal methods enable us to provide nearly optimal heuristics and strategies for register optimization in the face of ILP.