Ultrafast Single Error Correction Codes for Protecting Processor Registers

In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit precomputation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weightcolumn code during the write operation and is designed by replacing 0’s with 1’s at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the oddweight-column code, the implementation based on the proposed SEC-DED code with check bit precomputation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.

Error control coding improves reliability and efficiency of wireless communication systems. This research delves into the latest advancements in error control coding schemes for wireless communication systems, with a specific focus on their application within the domain of Low Power Wide Area Networks (LPWANs) such as Narrowband Internet of Things (NB-IoT) systems, LoRa energy-efficient hardware design, random access control systems, and wireless sensor networks. In the context of LPWANs, particularly NB-IoT systems, we investigate the adaptive coding and modulation (ACM) in NB-IoT systems, which adapts coding rates and modulation techniques to changing channel circumstances. Comprehensive analysis of the literature review shows that the proposed approaches are more energy efficient and less error-prone than fixed coding and modulation schemes. Using Cell Design Methodology (CDM), Single Error Correction (SEC) codes are optimized for energy efficiency. Power and energy efficiency have improved in standard CMOS and CDM logic systems. This impacts IoT devices, memory storage, and security systems. Next, Forward Error Correction (FEC) is examined for ALOHA-based random-access control systems wherein packet loss rate and spectral efficiency metrics are mathematically calculated. FEC is beneficial, especially when time and frequency synchronization diverge. Monte Carlo simulations studied in the literature shows that FEC improves satellite communication systems. This review establishes benefits of FEC, notably in satellite communications systems. In addition, Wireless Sensor Networks (WSNs) error control techniques and network reliability and performance are examined along with Convolutional, Turbo, Low density parity check codes(LDPC), and Polar error correction coding (ECC) methods. We learn about their benefits, drawbacks, and implementation challenges by assessing their efficacy, efficiency, and applicability in wireless sensor networks (WSN) applications. This study further highlights advancements of energy-efficient error control coding when, integrated into network designs alongwith the trade-offs between efficacy and intricacy to help improve wireless communication networks. Finally, this study summarizes current error control coding approaches for wireless communication systems. We provide insights into improving reliability, energy conservation, and efficacy by examining ACM, CDM, FEC, and error correction coding (ECC) across varied domains including LPWAN and IoT technologies with earnest hope to facilitate researchers, engineers, and professionals working in the field of error control coding in wireless communication.

Soft errors caused by radiation particles are becoming an increasingly important issue for memory reliability. Traditionally, Single Error Correction (SEC) codes have been used to correct soft errors. Such codes can correct one error per memory word, but as errors become more frequent they may be insufficient. More complex error correction codes (ECCs) could be used, but they typically require complex decoders which impact memory area and speed. In this paper, the use of Euclidean geometry (EG) Codes for memory applications is studied. The results show that these codes, which provide powerful error correction capabilities, can be implemented efficiently in terms of area and latency.

Efficient error detection in Double Error Correction BCH codes for memory applications

Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes

To improve data reliability in NoC, extensively adopted method is the deployment of error correction codes. Errors present in the data flit are corrected by these codes and this is not applicable for correcting errors present in the header flit. So, there is a need for an coding method which will correct errors in data and also the header flit. Further, it is important to have a coding method that will decode the header flit faster compared to data flit, as header flit is used for processing the data flits. Existing single error correction and double error detection code is improved and presented in this paper to support faster error correction in header flit with retaining the same number of redundant bits. This improved code is synthesised and results are compared with existing code. The results show that the header flit are decoded faster compared to data flits as the critical path delay is reduced.

As the size of on-chip SRAM caches is increasing rapidly and the physical dimension of the SRAM devices is decreasing, reliability of caches is becoming a growing concern. This is because with increased size of caches, the likelihood of radiation-induced soft faults also increases. As a result, information redundancy in the form of Error Correcting Codes (ECC) is becoming extremely important, especially to protect the larger sized last level caches (LLCs). In typical ECCs, extra redundancy bits are added to every row to detect and correct errors. There is additional encoding (while writing data) and decoding (while reading data) procedures required as well. In caches, these additional area, power and latency overheads need to be minimized as much as possible. To address this problem, we present in this paper Parity++: a novel unequal message protection scheme for last level caches that preferentially provides stronger error protection to certain "special messages". This protection scheme provides Single Error Detection (SED) for all messages and Single Error Correction (SEC) for a subset of messages. Thus, it is stronger than just a basic SED parity and has much lower parity storage overhead (4X lower for a 64-bit memory) and lower error detection energy than a traditional Single Error Correcting, Double Error Detecting (SECDED) code. We also evaluate Parity++ with a memory speculation procedure that can be used with any ECC scheme to hide the decoding latency while reading messages when there are no errors.

Error-correcting codes (ECC) are widely used during data transfer in wireless communication systems as well as in computer memory architectures. The error-correcting process is based on sending data with extra parity bits and decoding the received data for error correction. The first error detection and correction code, introduced in 1950, Hamming Code (7,4) is a linear error-correcting code able to detect and correct a single-bit error by encoding 7-bit data from 4-bit data, including 3 parity bits. Previous efforts using unipolar resistive random access memory (ReRAM) based in-memory computation of Hamming Code (7,4) resulted in 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> times lower power consumption compared to GPU and 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> times less than CPU-based computations. However further reduction of power consumption can be achieved by vector-matrix multiplication (VMM) using bipolar ReRAM arrays. In the VMM based approach, an encoding or decoding code matrix is stored in the array where it leverages the nonvolatile properties of ReRAM. With the VMM approach, the total number of computation cycles is not limited by the endurance of the ReRAM devices. Here we report the first experimental results of encoding and decoding Hamming code (7,4) using 1 transistor 1 hafnium oxide-based ReRAM (1T1R) arrays fabricated using 65nm CMOS technology. Our results show bipolar 1T1R arrays can correctly encode 4-bit message data to 7 bit encoded data as well as error position detection with overall 3 fold less power consumption than previously reported unipolar ReRAM crossbar array-based computation. Furthermore, we propose and simulate a peripheral circuit to convert the analog column output from a 1T1R array to single-bit binary output using the Cadence Spectre simulator. Our results pave the way for using a memristor-based fast and scalable hardware solution for encoding decoding of error-correcting codes

Single error correction (SEC) codes are widely used to protect data stored in memories and registers. In some applications, such as networking, a few control bits are added to the data to facilitate their processing. For example, flags to mark the start or the end of a packet are widely used. Therefore, it is important to have SEC codes that protect both the data and the associated control bits. It is attractive for these codes to provide fast decoding of the control bits, as these are used to determine the processing of the data and are commonly on the critical timing path. In this brief, a method to extend SEC codes to support a few additional control bits is presented. The derived codes support fast decoding of the additional control bits and are therefore suitable for networking applications.

Soft errors have been a concern in memories for many years. In older technologies, soft errors typically affected a single memory cell but as technology scaled, Multiple Cell Upsets (MCUs) that affect a group of nearby cells have become more common. This trend is expected to continue making MCUs more frequent and also increasing the number of cells affected. To avoid data corruption in memories, Error Correction Codes (ECCs) are used. Single Error Correction (SEC) codes that can correct one bit error per word are effective only against single errors. To protect against MCUs, one option is to use more sophisticated error correction codes like for example, Orthogonal Latin Squares Codes (OLSC). In this paper, a modification of the OLSC decoding algorithm is proposed for codes that can correct two random errors. This modification has little impact on circuit complexity and enables triple adjacent error correction which is interesting when MCUs are present.

We are developing a 32-bit embedded processor core with soft error detection and recovery mechanisms. Adding a parity bit into pipeline registers makes it possible to detect single event upset in an processor core. Detection of 2-bit and less multiple bit upset and automatic correction of single event upset can be done with single error correction and double error detection code. These soft-error detection/recovery mechanisms cause cost/performance degradation. In this paper, probability of serious calculation failures occurred by SEU in an MIPS R3000 compatible processor core is evaluated. We investigate the probability using register transfer level simulation. The result shows that impacts of SEU to calculation result differ much, when SEU happens in a program counter, an instruction register or register files. Soft error detection/recovery mechanism of an embedded processor core can be selected automatically when permitted soft error rate of an application program is given as a specification.

Due to scaling in CMOS technology, multiple bit upsets (MBUs) have been widely occurred in memories. As a result, multiple adjacent bits of memories are corrupted and valuable information are lost forever. To mitigate these problems, multi-bit adjacent error-correcting codes are generally employed in SRAM memories. Single error correction-double error detection-double adjacent error correction (SEC-DED-DAEC) codes are used to mitigate radiation or noise source induced MBUs to protect static random access memory (SRAM) devices. These codes are able to correct single and double adjacent errors, and also detect double errors. In this paper, three different SEC-DED-DAEC codes have been designed and implemented for SRAM memories. All functional blocks of these codecs are simulated and synthesized both in FPGA and ASIC platforms. Performances of the different SEC-DED-DAEC codes are observed in terms of area and delay.

In Ultra Deep Sub Micron (UDSM) Technology, accomplishment of error free data transmission through Network on Chip (NoC) interconnect becomes impractical. This difficult state is widely managed by the use of Error Correction Codes (ECC) in NoC. A novel Hamming based Multiple Transient Error Correction (HMTEC) code is proposed to enhance the NoC interconnect reliability. Implementation of this code corrects all single bit errors and most of the combinations of errors upto 8 bits for a flit size of 32. Furthermore, this code allows error correction in both data and redundant bits. This coding method is performed at lower power consumption, area occupancy and delay when measured against similar codes proposed in recent years.

Increasing process variations coupled with aggressive scaling of cell area and operating voltage in the quest of higher density and lower power have greatly affected the reliability of on-chip memory. Error correction code (ECC) has been traditionally used inside memory to provide uniform protection to all bits in a code word. They suffer from either adequate protection against multibit failures or large overhead due to encoding/decoding logic and parity bits. To address this issue, we present a variable data-length ECC (VL-ECC) for the embedded memory devices of digital signal processors, in which the data length of ECC can be dynamically reconfigured to preferentially protect the relatively more important bits. In the proposed VL-ECC, when the number of failures exceeds the error correction capability, the data length of ECC is reduced to focus on the relatively more important higher order data bit parts, thereby minimizing system quality degradation due to bit failures. When the proposed VL-ECC is applied to the embedded memory devices of an H.264 processor, average peak signal-to-noise-ratio improvements of up to 5.12 dB are achieved compared with the conventional ECC under supply voltage of 800 mV or lower. With the fast Fourier transform processor, signal-to-quantization noise ratio is improved by up to 5.2 dB.

In recent years, there has been a growing interest in error correction codes (ECCs) that can correct localized errors in memories. This is due to the larger fraction of radiation induced error events that affect several nearby memory cells as technology scales. Initially, codes that can correct single and double adjacent errors were proposed. More recently, 3-bit burst ECCs have also been presented. The next step is to provide efficient 4-bit burst error correction for memories. The issue is that as the error correction capability increases so does the overheads required to implement the codes in terms of parity check bits and encoding and decoding complexity. In this brief, efficient solutions to protect memories against 4-bit bursts are presented. The first one is the use of two interleaved single and double adjacent ECC while in the second, efficient 4-bit burst ECCs are presented. The first solution reduces the decoding complexity and delay at the cost of having more parity check bits while the second tries to reduce the decoding complexity when using the minimum number of parity check bits. Both solutions have been evaluated and compared to an interleaved single error correction code and with existing burst ECCs to better understand the overheads needed to achieve the protection against 4-bit burst errors.