Efficient error detection in Double Error Correction BCH codes for memory applications

Error control coding improves reliability and efficiency of wireless communication systems. This research delves into the latest advancements in error control coding schemes for wireless communication systems, with a specific focus on their application within the domain of Low Power Wide Area Networks (LPWANs) such as Narrowband Internet of Things (NB-IoT) systems, LoRa energy-efficient hardware design, random access control systems, and wireless sensor networks. In the context of LPWANs, particularly NB-IoT systems, we investigate the adaptive coding and modulation (ACM) in NB-IoT systems, which adapts coding rates and modulation techniques to changing channel circumstances. Comprehensive analysis of the literature review shows that the proposed approaches are more energy efficient and less error-prone than fixed coding and modulation schemes. Using Cell Design Methodology (CDM), Single Error Correction (SEC) codes are optimized for energy efficiency. Power and energy efficiency have improved in standard CMOS and CDM logic systems. This impacts IoT devices, memory storage, and security systems. Next, Forward Error Correction (FEC) is examined for ALOHA-based random-access control systems wherein packet loss rate and spectral efficiency metrics are mathematically calculated. FEC is beneficial, especially when time and frequency synchronization diverge. Monte Carlo simulations studied in the literature shows that FEC improves satellite communication systems. This review establishes benefits of FEC, notably in satellite communications systems. In addition, Wireless Sensor Networks (WSNs) error control techniques and network reliability and performance are examined along with Convolutional, Turbo, Low density parity check codes(LDPC), and Polar error correction coding (ECC) methods. We learn about their benefits, drawbacks, and implementation challenges by assessing their efficacy, efficiency, and applicability in wireless sensor networks (WSN) applications. This study further highlights advancements of energy-efficient error control coding when, integrated into network designs alongwith the trade-offs between efficacy and intricacy to help improve wireless communication networks. Finally, this study summarizes current error control coding approaches for wireless communication systems. We provide insights into improving reliability, energy conservation, and efficacy by examining ACM, CDM, FEC, and error correction coding (ECC) across varied domains including LPWAN and IoT technologies with earnest hope to facilitate researchers, engineers, and professionals working in the field of error control coding in wireless communication.

Error correction codes (ECCs) are commonly used in computer systems to protect information from errors. For example, single error correction (SEC) codes are frequently used for memory protection. Due to continuous technology scaling, soft errors on registers have become a major concern, and ECCs are required to protect them. Nevertheless, using an ECC increases delay, area and power consumption. In this way, ECCs are traditionally designed focusing on minimizing the number of redundant bits added. This is important in memories, as these bits are added to each word in the whole memory. However, this fact is less important in registers, where minimizing the encoding and decoding delay can be more interesting. This paper proposes a method to develop codes with 1-gate delay encoders and 4-gate delay decoders, independently of the word length. These codes have been designed to correct single errors only in data bits to reduce the overhead.

In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit precomputation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weightcolumn code during the write operation and is designed by replacing 0’s with 1’s at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the oddweight-column code, the implementation based on the proposed SEC-DED code with check bit precomputation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.

Error-correcting codes (ECC) are widely used during data transfer in wireless communication systems as well as in computer memory architectures. The error-correcting process is based on sending data with extra parity bits and decoding the received data for error correction. The first error detection and correction code, introduced in 1950, Hamming Code (7,4) is a linear error-correcting code able to detect and correct a single-bit error by encoding 7-bit data from 4-bit data, including 3 parity bits. Previous efforts using unipolar resistive random access memory (ReRAM) based in-memory computation of Hamming Code (7,4) resulted in 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> times lower power consumption compared to GPU and 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> times less than CPU-based computations. However further reduction of power consumption can be achieved by vector-matrix multiplication (VMM) using bipolar ReRAM arrays. In the VMM based approach, an encoding or decoding code matrix is stored in the array where it leverages the nonvolatile properties of ReRAM. With the VMM approach, the total number of computation cycles is not limited by the endurance of the ReRAM devices. Here we report the first experimental results of encoding and decoding Hamming code (7,4) using 1 transistor 1 hafnium oxide-based ReRAM (1T1R) arrays fabricated using 65nm CMOS technology. Our results show bipolar 1T1R arrays can correctly encode 4-bit message data to 7 bit encoded data as well as error position detection with overall 3 fold less power consumption than previously reported unipolar ReRAM crossbar array-based computation. Furthermore, we propose and simulate a peripheral circuit to convert the analog column output from a 1T1R array to single-bit binary output using the Cadence Spectre simulator. Our results pave the way for using a memristor-based fast and scalable hardware solution for encoding decoding of error-correcting codes

Soft errors caused by radiation particles are becoming an increasingly important issue for memory reliability. Traditionally, Single Error Correction (SEC) codes have been used to correct soft errors. Such codes can correct one error per memory word, but as errors become more frequent they may be insufficient. More complex error correction codes (ECCs) could be used, but they typically require complex decoders which impact memory area and speed. In this paper, the use of Euclidean geometry (EG) Codes for memory applications is studied. The results show that these codes, which provide powerful error correction capabilities, can be implemented efficiently in terms of area and latency.

Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes

Single error correction (SEC) codes are widely used to protect data stored in memories and registers. In some applications, such as networking, a few control bits are added to the data to facilitate their processing. For example, flags to mark the start or the end of a packet are widely used. Therefore, it is important to have SEC codes that protect both the data and the associated control bits. It is attractive for these codes to provide fast decoding of the control bits, as these are used to determine the processing of the data and are commonly on the critical timing path. In this brief, a method to extend SEC codes to support a few additional control bits is presented. The derived codes support fast decoding of the additional control bits and are therefore suitable for networking applications.

As the size of on-chip SRAM caches is increasing rapidly and the physical dimension of the SRAM devices is decreasing, reliability of caches is becoming a growing concern. This is because with increased size of caches, the likelihood of radiation-induced soft faults also increases. As a result, information redundancy in the form of Error Correcting Codes (ECC) is becoming extremely important, especially to protect the larger sized last level caches (LLCs). In typical ECCs, extra redundancy bits are added to every row to detect and correct errors. There is additional encoding (while writing data) and decoding (while reading data) procedures required as well. In caches, these additional area, power and latency overheads need to be minimized as much as possible. To address this problem, we present in this paper Parity++: a novel unequal message protection scheme for last level caches that preferentially provides stronger error protection to certain "special messages". This protection scheme provides Single Error Detection (SED) for all messages and Single Error Correction (SEC) for a subset of messages. Thus, it is stronger than just a basic SED parity and has much lower parity storage overhead (4X lower for a 64-bit memory) and lower error detection energy than a traditional Single Error Correcting, Double Error Detecting (SECDED) code. We also evaluate Parity++ with a memory speculation procedure that can be used with any ECC scheme to hide the decoding latency while reading messages when there are no errors.

Multi-level cell (MLC) NAND flash memories are very popular storage media because of their power efficiency and big storage density. This paper proposes to use nonlinear t-error-correcting codes to replace linear BCH codes for error detection and correction in MLC NAND flash memories. Compared to linear BCH codes with the same bit-error correcting capability t, the proposed codes have less errors miscorrected by all codewords and nearly no undetectable errors. For example, the proposed (8281, 8201, 11) 5-error-correcting code has no errors of multiplicity six miscorrected by all codewords while the widely used (8262, 8192, 11) linear shortened BCH code has 11 over 6 × A 11 errors in this class, where A 11 ≈ 1014 is the number of codewords of Hamming weight eleven in the shortened BCH code. Moreover, in spite of the fact that the Hamming distance of the proposed code is 2t+1, it can also correct some errors of multiplicity t+1 and t+2 requiring no extra hardware overhead and latency penalty. In this paper, the constructions and the error correction algorithm for the nonlinear t-error-correcting codes are presented. The architecture of the encoder and the decoder for the codes are shown. The error correcting capabilities, the hardware overhead, the latency and the power consumption for the encoder and the decoder will be analyzed and compared to that of the linear BCH codes to demonstrate the advantages of the proposed codes for error detection and correction in MLC NAND flash memories.

Generally in every communication medium, error correction codes were employed for correcting the obtained errors that are caused in the data due to transmission. The essence of these codes is to add redundant bits using mathematical algorithms at the transmission end and decode the received data to retrieve the original data. This paper presents the design of a Multi bit Error Detection and Correction (MEDC) system which is utilized in the microprocessors along with memory that performs error detection as well as error correction of data which was written and was read from memory using Bose, Ray-Chaudhuri, Hocquenghem (BCH) codes. The proposed MEDC system is synthesized and also simulated through Vivado design suit 2018.3 and was implemented using Kintex-7 FPGA board. Compared with the obtained results with well-known error detection codes, the proposed method is utilized for improving the performance, increase the rate of the error detection and correction in the transmitted data.

In recent years, there has been a growing interest in multi-bit error correction codes (ECCs) to protect SRAM memories. This has been caused by the increased number of multiple errors that memories suffer as technology scales. To be suitable to protect an SRAM memory, an ECC has to be decodable in parallel and with low latency. Among the codes proposed for memory protection are orthogonal latin square (OLS) codes that provide low latency decoding and a modular construction. For some applications, like multimedia or signal processing, the effect of errors on the memory bits can be very different depending on their position on the word. Therefore, in these cases, it is more effective to provide different degrees of error correction for the different bits. This is done with unequal error protection (UEP) codes. In this paper, UEP codes are derived from double error correction (DEC) OLS codes. The derived codes are implemented for an FPGA platform to evaluate the decoder complexity and latency. The results show that the new codes can be implemented with lower decoding delay than traditional SEC-DED codes and with a cost similar to that of both DEC OLS and SEC-DED codes.

To improve data reliability in NoC, extensively adopted method is the deployment of error correction codes. Errors present in the data flit are corrected by these codes and this is not applicable for correcting errors present in the header flit. So, there is a need for an coding method which will correct errors in data and also the header flit. Further, it is important to have a coding method that will decode the header flit faster compared to data flit, as header flit is used for processing the data flits. Existing single error correction and double error detection code is improved and presented in this paper to support faster error correction in header flit with retaining the same number of redundant bits. This improved code is synthesised and results are compared with existing code. The results show that the header flit are decoded faster compared to data flits as the critical path delay is reduced.

Soft errors have been a concern in memories for many years. In older technologies, soft errors typically affected a single memory cell but as technology scaled, Multiple Cell Upsets (MCUs) that affect a group of nearby cells have become more common. This trend is expected to continue making MCUs more frequent and also increasing the number of cells affected. To avoid data corruption in memories, Error Correction Codes (ECCs) are used. Single Error Correction (SEC) codes that can correct one bit error per word are effective only against single errors. To protect against MCUs, one option is to use more sophisticated error correction codes like for example, Orthogonal Latin Squares Codes (OLSC). In this paper, a modification of the OLSC decoding algorithm is proposed for codes that can correct two random errors. This modification has little impact on circuit complexity and enables triple adjacent error correction which is interesting when MCUs are present.

Many of the modern computer memories contain single-error correction capability in order to enhance reliability. In a large scale memory, an even more powerful error correction code may be desirable. In particular, a double-error correction capability can reduce the maintenance cost significantly, while keeping the unscheduled system interruptions within tolerable limits. Since most faults are effectively masked and logged out, the permanent failures can be replaced at the time of scheduled maintenance, thus leaving the user unaffected. The cost and complexity of the known double error correcting code, however, seems to outweigh the advantages. The long decoding time and large amount of redundancy in double error correction cannot be justified in every fetch instruction for the sake of correcting an occasional double error.

Error correction codes are used in semiconductor memories to protect information against errors. Simple error correction codes are preferred due to their low redundancy and encoding/decoding latency. Hamming codes are simple and can be easily built for any word length. They only allow single error correction, so a multiple error can lead to a wrong decoding. Multiple errors often manifest as burst errors, and they are becoming more frequent as integration scale increases. This paper proposes modified Hamming codes, with the same redundancy and coverage as the original versions, but adding short burst error detection. Three code examples, with different error correction and detection capabilities, are presented. They are especially well-suited for memories, where the length of the data word is commonly a power of 2, and low redundancy and fast and simple encoder and decoder circuits are required.