Fast Error Correction for Header Flit in NoC

In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit precomputation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weightcolumn code during the write operation and is designed by replacing 0’s with 1’s at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the oddweight-column code, the implementation based on the proposed SEC-DED code with check bit precomputation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.

Error correction codes (ECCs) are commonly used in computer systems to protect information from errors. For example, single error correction (SEC) codes are frequently used for memory protection. Due to continuous technology scaling, soft errors on registers have become a major concern, and ECCs are required to protect them. Nevertheless, using an ECC increases delay, area and power consumption. In this way, ECCs are traditionally designed focusing on minimizing the number of redundant bits added. This is important in memories, as these bits are added to each word in the whole memory. However, this fact is less important in registers, where minimizing the encoding and decoding delay can be more interesting. This paper proposes a method to develop codes with 1-gate delay encoders and 4-gate delay decoders, independently of the word length. These codes have been designed to correct single errors only in data bits to reduce the overhead.

We are developing a 32-bit embedded processor core with soft error detection and recovery mechanisms. Adding a parity bit into pipeline registers makes it possible to detect single event upset in an processor core. Detection of 2-bit and less multiple bit upset and automatic correction of single event upset can be done with single error correction and double error detection code. These soft-error detection/recovery mechanisms cause cost/performance degradation. In this paper, probability of serious calculation failures occurred by SEU in an MIPS R3000 compatible processor core is evaluated. We investigate the probability using register transfer level simulation. The result shows that impacts of SEU to calculation result differ much, when SEU happens in a program counter, an instruction register or register files. Soft error detection/recovery mechanism of an embedded processor core can be selected automatically when permitted soft error rate of an application program is given as a specification.

Error control coding improves reliability and efficiency of wireless communication systems. This research delves into the latest advancements in error control coding schemes for wireless communication systems, with a specific focus on their application within the domain of Low Power Wide Area Networks (LPWANs) such as Narrowband Internet of Things (NB-IoT) systems, LoRa energy-efficient hardware design, random access control systems, and wireless sensor networks. In the context of LPWANs, particularly NB-IoT systems, we investigate the adaptive coding and modulation (ACM) in NB-IoT systems, which adapts coding rates and modulation techniques to changing channel circumstances. Comprehensive analysis of the literature review shows that the proposed approaches are more energy efficient and less error-prone than fixed coding and modulation schemes. Using Cell Design Methodology (CDM), Single Error Correction (SEC) codes are optimized for energy efficiency. Power and energy efficiency have improved in standard CMOS and CDM logic systems. This impacts IoT devices, memory storage, and security systems. Next, Forward Error Correction (FEC) is examined for ALOHA-based random-access control systems wherein packet loss rate and spectral efficiency metrics are mathematically calculated. FEC is beneficial, especially when time and frequency synchronization diverge. Monte Carlo simulations studied in the literature shows that FEC improves satellite communication systems. This review establishes benefits of FEC, notably in satellite communications systems. In addition, Wireless Sensor Networks (WSNs) error control techniques and network reliability and performance are examined along with Convolutional, Turbo, Low density parity check codes(LDPC), and Polar error correction coding (ECC) methods. We learn about their benefits, drawbacks, and implementation challenges by assessing their efficacy, efficiency, and applicability in wireless sensor networks (WSN) applications. This study further highlights advancements of energy-efficient error control coding when, integrated into network designs alongwith the trade-offs between efficacy and intricacy to help improve wireless communication networks. Finally, this study summarizes current error control coding approaches for wireless communication systems. We provide insights into improving reliability, energy conservation, and efficacy by examining ACM, CDM, FEC, and error correction coding (ECC) across varied domains including LPWAN and IoT technologies with earnest hope to facilitate researchers, engineers, and professionals working in the field of error control coding in wireless communication.

In this paper, we study basic properties of linear network error correction codes, their construction and error correction capability for various kinds of errors. Our discussion is restricted to the single-source multicast case. We define the minimum distance of a network error correction code. This plays the same role as it does in classical coding theory. We construct codes that can correct errors up to the full error correction capability specified by Singleton bound for network error correction codes recently established by Cai and Yeung. We propose a decoding principle for network error correction codes, based on which we introduce two decoding algorithms and analyze their performance. We formulate the global kernel error correction problem and characterize the error correction capability of codes for this kind of error.

Soft errors caused by radiation particles are becoming an increasingly important issue for memory reliability. Traditionally, Single Error Correction (SEC) codes have been used to correct soft errors. Such codes can correct one error per memory word, but as errors become more frequent they may be insufficient. More complex error correction codes (ECCs) could be used, but they typically require complex decoders which impact memory area and speed. In this paper, the use of Euclidean geometry (EG) Codes for memory applications is studied. The results show that these codes, which provide powerful error correction capabilities, can be implemented efficiently in terms of area and latency.

The transmission of communication signals must not only ensure the speed of transmission, but also ensure the accuracy of transmission. The current research has been able to draw the advantages and disadvantages of the application of different error-correcting codes. However, it is not enough to simply compare transmission performance between different error correction code applications. Therefore, this paper uses MATLAB to simulate the transmission environment of the real channel, analyzes the reception error of short-length data through QPSK coding and IQ modulation, and analyzes the signal transmission using error correction code (Hamming code) and error detection code (even check code). The transmission performances were explored and compared, and their anti-noise interference performance was analyzed. Studies have shown that for short-length data, the error correction method using Hamming code can resist limited noise interference, but it can save bandwidth and increase the proportion of effective signal bits. In the low signal-to-noise ratio case, the method of using even-check code to detect errors has problems. Errors may be generated, and the proportion of effective signal bits is low, but the adaptability to noise is stronger than the previous method. Therefore, it is recommended to select different transmission methods for transmission environments with different signal-to-noise ratio ranges, and the combination of the two may further improve the anti-noise interference capability of signal transmission.

Error-correcting codes (ECC) are widely used during data transfer in wireless communication systems as well as in computer memory architectures. The error-correcting process is based on sending data with extra parity bits and decoding the received data for error correction. The first error detection and correction code, introduced in 1950, Hamming Code (7,4) is a linear error-correcting code able to detect and correct a single-bit error by encoding 7-bit data from 4-bit data, including 3 parity bits. Previous efforts using unipolar resistive random access memory (ReRAM) based in-memory computation of Hamming Code (7,4) resulted in 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> times lower power consumption compared to GPU and 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> times less than CPU-based computations. However further reduction of power consumption can be achieved by vector-matrix multiplication (VMM) using bipolar ReRAM arrays. In the VMM based approach, an encoding or decoding code matrix is stored in the array where it leverages the nonvolatile properties of ReRAM. With the VMM approach, the total number of computation cycles is not limited by the endurance of the ReRAM devices. Here we report the first experimental results of encoding and decoding Hamming code (7,4) using 1 transistor 1 hafnium oxide-based ReRAM (1T1R) arrays fabricated using 65nm CMOS technology. Our results show bipolar 1T1R arrays can correctly encode 4-bit message data to 7 bit encoded data as well as error position detection with overall 3 fold less power consumption than previously reported unipolar ReRAM crossbar array-based computation. Furthermore, we propose and simulate a peripheral circuit to convert the analog column output from a 1T1R array to single-bit binary output using the Cadence Spectre simulator. Our results pave the way for using a memristor-based fast and scalable hardware solution for encoding decoding of error-correcting codes

Efficient error detection in Double Error Correction BCH codes for memory applications

Single error correction (SEC) codes are widely used to protect data stored in memories and registers. In some applications, such as networking, a few control bits are added to the data to facilitate their processing. For example, flags to mark the start or the end of a packet are widely used. Therefore, it is important to have SEC codes that protect both the data and the associated control bits. It is attractive for these codes to provide fast decoding of the control bits, as these are used to determine the processing of the data and are commonly on the critical timing path. In this brief, a method to extend SEC codes to support a few additional control bits is presented. The derived codes support fast decoding of the additional control bits and are therefore suitable for networking applications.

Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes

As the size of on-chip SRAM caches is increasing rapidly and the physical dimension of the SRAM devices is decreasing, reliability of caches is becoming a growing concern. This is because with increased size of caches, the likelihood of radiation-induced soft faults also increases. As a result, information redundancy in the form of Error Correcting Codes (ECC) is becoming extremely important, especially to protect the larger sized last level caches (LLCs). In typical ECCs, extra redundancy bits are added to every row to detect and correct errors. There is additional encoding (while writing data) and decoding (while reading data) procedures required as well. In caches, these additional area, power and latency overheads need to be minimized as much as possible. To address this problem, we present in this paper Parity++: a novel unequal message protection scheme for last level caches that preferentially provides stronger error protection to certain "special messages". This protection scheme provides Single Error Detection (SED) for all messages and Single Error Correction (SEC) for a subset of messages. Thus, it is stronger than just a basic SED parity and has much lower parity storage overhead (4X lower for a 64-bit memory) and lower error detection energy than a traditional Single Error Correcting, Double Error Detecting (SECDED) code. We also evaluate Parity++ with a memory speculation procedure that can be used with any ECC scheme to hide the decoding latency while reading messages when there are no errors.

Generally in every communication medium, error correction codes were employed for correcting the obtained errors that are caused in the data due to transmission. The essence of these codes is to add redundant bits using mathematical algorithms at the transmission end and decode the received data to retrieve the original data. This paper presents the design of a Multi bit Error Detection and Correction (MEDC) system which is utilized in the microprocessors along with memory that performs error detection as well as error correction of data which was written and was read from memory using Bose, Ray-Chaudhuri, Hocquenghem (BCH) codes. The proposed MEDC system is synthesized and also simulated through Vivado design suit 2018.3 and was implemented using Kintex-7 FPGA board. Compared with the obtained results with well-known error detection codes, the proposed method is utilized for improving the performance, increase the rate of the error detection and correction in the transmitted data.

In Ultra Deep Sub Micron (UDSM) Technology, accomplishment of error free data transmission through Network on Chip (NoC) interconnect becomes impractical. This difficult state is widely managed by the use of Error Correction Codes (ECC) in NoC. A novel Hamming based Multiple Transient Error Correction (HMTEC) code is proposed to enhance the NoC interconnect reliability. Implementation of this code corrects all single bit errors and most of the combinations of errors upto 8 bits for a flit size of 32. Furthermore, this code allows error correction in both data and redundant bits. This coding method is performed at lower power consumption, area occupancy and delay when measured against similar codes proposed in recent years.

Maximum distance separable (MDS) codes are those codes whose minimum distance attains the Singleton bound for a given length and given dimension. It is a well-known fact that the only binary linear block codes that are MDS are the simple parity codes and the repetition codes. Known MDS codes (the Reed-Solomon codes, for instance) are defined over larger alphabets. This approach requires that (i) the encoding and decoding procedures are performed as operations over a finite field and (ii) an update in a single information bit (e.g. in storage applications) requires an update in the redundancy symbols and usually affects a number of bits in each redundancy symbol. Thus, the optimal redundancy is achieved at the expense of additional complexity in the encoding/decoding procedures as well as in the number of redundancy bits affected by an update in the information. We construct MDS codes that have the following two properties: (i) the redundancy bits are computed by simple XOR operations; and (ii) an update in an information bit affects a minimal number of redundancy bits. >