Efficient Implementations of 4-Bit Burst Error Correction for Memories

Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes

Due to scaling in CMOS technology, multiple bit upsets (MBUs) have been widely occurred in memories. As a result, multiple adjacent bits of memories are corrupted and valuable information are lost forever. To mitigate these problems, multi-bit adjacent error-correcting codes are generally employed in SRAM memories. Single error correction-double error detection-double adjacent error correction (SEC-DED-DAEC) codes are used to mitigate radiation or noise source induced MBUs to protect static random access memory (SRAM) devices. These codes are able to correct single and double adjacent errors, and also detect double errors. In this paper, three different SEC-DED-DAEC codes have been designed and implemented for SRAM memories. All functional blocks of these codecs are simulated and synthesized both in FPGA and ASIC platforms. Performances of the different SEC-DED-DAEC codes are observed in terms of area and delay.

In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit precomputation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weightcolumn code during the write operation and is designed by replacing 0’s with 1’s at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the oddweight-column code, the implementation based on the proposed SEC-DED code with check bit precomputation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.

Error correction codes (ECCs) are commonly used in computer systems to protect information from errors. For example, single error correction (SEC) codes are frequently used for memory protection. Due to continuous technology scaling, soft errors on registers have become a major concern, and ECCs are required to protect them. Nevertheless, using an ECC increases delay, area and power consumption. In this way, ECCs are traditionally designed focusing on minimizing the number of redundant bits added. This is important in memories, as these bits are added to each word in the whole memory. However, this fact is less important in registers, where minimizing the encoding and decoding delay can be more interesting. This paper proposes a method to develop codes with 1-gate delay encoders and 4-gate delay decoders, independently of the word length. These codes have been designed to correct single errors only in data bits to reduce the overhead.

Error control coding improves reliability and efficiency of wireless communication systems. This research delves into the latest advancements in error control coding schemes for wireless communication systems, with a specific focus on their application within the domain of Low Power Wide Area Networks (LPWANs) such as Narrowband Internet of Things (NB-IoT) systems, LoRa energy-efficient hardware design, random access control systems, and wireless sensor networks. In the context of LPWANs, particularly NB-IoT systems, we investigate the adaptive coding and modulation (ACM) in NB-IoT systems, which adapts coding rates and modulation techniques to changing channel circumstances. Comprehensive analysis of the literature review shows that the proposed approaches are more energy efficient and less error-prone than fixed coding and modulation schemes. Using Cell Design Methodology (CDM), Single Error Correction (SEC) codes are optimized for energy efficiency. Power and energy efficiency have improved in standard CMOS and CDM logic systems. This impacts IoT devices, memory storage, and security systems. Next, Forward Error Correction (FEC) is examined for ALOHA-based random-access control systems wherein packet loss rate and spectral efficiency metrics are mathematically calculated. FEC is beneficial, especially when time and frequency synchronization diverge. Monte Carlo simulations studied in the literature shows that FEC improves satellite communication systems. This review establishes benefits of FEC, notably in satellite communications systems. In addition, Wireless Sensor Networks (WSNs) error control techniques and network reliability and performance are examined along with Convolutional, Turbo, Low density parity check codes(LDPC), and Polar error correction coding (ECC) methods. We learn about their benefits, drawbacks, and implementation challenges by assessing their efficacy, efficiency, and applicability in wireless sensor networks (WSN) applications. This study further highlights advancements of energy-efficient error control coding when, integrated into network designs alongwith the trade-offs between efficacy and intricacy to help improve wireless communication networks. Finally, this study summarizes current error control coding approaches for wireless communication systems. We provide insights into improving reliability, energy conservation, and efficacy by examining ACM, CDM, FEC, and error correction coding (ECC) across varied domains including LPWAN and IoT technologies with earnest hope to facilitate researchers, engineers, and professionals working in the field of error control coding in wireless communication.

Radiation-induced soft errors are a major reliability concern for memories. To ensure that memory contents are not corrupted, single error correction double error detection (SEC-DED) codes are commonly used, however, in advanced technology nodes, soft errors frequently affect more than one memory bit. Since SEC-DED codes cannot correct multiple errors, they are often combined with interleaving. Interleaving, however, impacts memory design and performance and cannot always be used in small memories. This limitation has spurred interest in codes that can correct adjacent bit errors. In particular, several SEC-DED double adjacent error correction (SEC-DED-DAEC) codes have recently been proposed. Implementing DAEC has a cost as it impacts the decoder complexity and delay. Another issue is that most of the new SEC-DED-DAEC codes miscorrect some double nonadjacent bit errors. In this brief, a new class of SEC-DED-DAEC codes is derived from orthogonal latin squares codes. The new codes significantly reduce the decoding complexity and delay. In addition, the codes do not miscorrect any double nonadjacent bit errors. The main disadvantage of the new codes is that they require a larger number of parity check bits. Therefore, they can be useful when decoding delay or complexity is critical or when miscorrection of double nonadjacent bit errors is not acceptable. The proposed codes have been implemented in Hardware Description Language and compared with some of the existing SEC-DED-DAEC codes. The results confirm the reduction in decoder delay.

Error-correcting codes (ECC) are widely used during data transfer in wireless communication systems as well as in computer memory architectures. The error-correcting process is based on sending data with extra parity bits and decoding the received data for error correction. The first error detection and correction code, introduced in 1950, Hamming Code (7,4) is a linear error-correcting code able to detect and correct a single-bit error by encoding 7-bit data from 4-bit data, including 3 parity bits. Previous efforts using unipolar resistive random access memory (ReRAM) based in-memory computation of Hamming Code (7,4) resulted in 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> times lower power consumption compared to GPU and 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> times less than CPU-based computations. However further reduction of power consumption can be achieved by vector-matrix multiplication (VMM) using bipolar ReRAM arrays. In the VMM based approach, an encoding or decoding code matrix is stored in the array where it leverages the nonvolatile properties of ReRAM. With the VMM approach, the total number of computation cycles is not limited by the endurance of the ReRAM devices. Here we report the first experimental results of encoding and decoding Hamming code (7,4) using 1 transistor 1 hafnium oxide-based ReRAM (1T1R) arrays fabricated using 65nm CMOS technology. Our results show bipolar 1T1R arrays can correctly encode 4-bit message data to 7 bit encoded data as well as error position detection with overall 3 fold less power consumption than previously reported unipolar ReRAM crossbar array-based computation. Furthermore, we propose and simulate a peripheral circuit to convert the analog column output from a 1T1R array to single-bit binary output using the Cadence Spectre simulator. Our results pave the way for using a memristor-based fast and scalable hardware solution for encoding decoding of error-correcting codes

Efficient error detection in Double Error Correction BCH codes for memory applications

Soft errors caused by radiation particles are becoming an increasingly important issue for memory reliability. Traditionally, Single Error Correction (SEC) codes have been used to correct soft errors. Such codes can correct one error per memory word, but as errors become more frequent they may be insufficient. More complex error correction codes (ECCs) could be used, but they typically require complex decoders which impact memory area and speed. In this paper, the use of Euclidean geometry (EG) Codes for memory applications is studied. The results show that these codes, which provide powerful error correction capabilities, can be implemented efficiently in terms of area and latency.

Soft errors have been a concern in memories for many years. In older technologies, soft errors typically affected a single memory cell but as technology scaled, Multiple Cell Upsets (MCUs) that affect a group of nearby cells have become more common. This trend is expected to continue making MCUs more frequent and also increasing the number of cells affected. To avoid data corruption in memories, Error Correction Codes (ECCs) are used. Single Error Correction (SEC) codes that can correct one bit error per word are effective only against single errors. To protect against MCUs, one option is to use more sophisticated error correction codes like for example, Orthogonal Latin Squares Codes (OLSC). In this paper, a modification of the OLSC decoding algorithm is proposed for codes that can correct two random errors. This modification has little impact on circuit complexity and enables triple adjacent error correction which is interesting when MCUs are present.

In recent years, there has been a growing interest in multi-bit error correction codes (ECCs) to protect SRAM memories. This has been caused by the increased number of multiple errors that memories suffer as technology scales. To be suitable to protect an SRAM memory, an ECC has to be decodable in parallel and with low latency. Among the codes proposed for memory protection are orthogonal latin square (OLS) codes that provide low latency decoding and a modular construction. For some applications, like multimedia or signal processing, the effect of errors on the memory bits can be very different depending on their position on the word. Therefore, in these cases, it is more effective to provide different degrees of error correction for the different bits. This is done with unequal error protection (UEP) codes. In this paper, UEP codes are derived from double error correction (DEC) OLS codes. The derived codes are implemented for an FPGA platform to evaluate the decoder complexity and latency. The results show that the new codes can be implemented with lower decoding delay than traditional SEC-DED codes and with a cost similar to that of both DEC OLS and SEC-DED codes.

Three-dimensional (3D) error correction coding (ECC) provides volumetrically coupled ECC blocks, the possible errors of which can be controlled powerfully by correcting errors from three different directions, iteratively. However, increased parities cause a large overhead, which limits the application of strong ECC schemes. In this study, a new efficient 3D ECC scheme and its decoding algorithm for holographic data storage were developed and evaluated. The proposed scheme has 3D ECC capability with a relatively low coding overhead, similarly to that of conventional 2D error correcting schemes, such as RSPC. It gives favorable ECC performance with a high efficiency in a page-based recording and retrieving system, which enables the use of a 3D ECC scheme for various applications.

Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically refreshed to retain data. Like SRAM, eDRAM is susceptible to device variations, which play a role in determining refresh time for eDRAM cells. Refresh power potentially represents a large fraction of overall system power, particularly during low-power states when the CPU is idle. Future designs need to reduce cache power without incurring the high cost of flushing cache data when entering low-power states. In this paper, we show the significant impact of variations on refresh time and cache power consumption for large eDRAM caches. We propose Hi-ECC, a technique that incorporates multi-bit error-correcting codes to significantly reduce refresh rate. Multi-bit error-correcting codes usually have a complex decoder design and high storage cost. Hi-ECC avoids the decoder complexity by using strong ECC codes to identify and disable sections of the cache with multi-bit failures, while providing efficient single-bit error correction for the common case. Hi-ECC includes additional optimizations that allow us to amortize the storage cost of the code over large data words, providing the benefit of multi-bit correction at same storage cost as a single-bit error-correcting (SECDED) code (2% overhead). Our proposal achieves a 93% reduction in refresh power vs. a baseline eDRAM cache without error correcting capability, and a 66% reduction in refresh power vs. a system using SECDED codes.

To improve data reliability in NoC, extensively adopted method is the deployment of error correction codes. Errors present in the data flit are corrected by these codes and this is not applicable for correcting errors present in the header flit. So, there is a need for an coding method which will correct errors in data and also the header flit. Further, it is important to have a coding method that will decode the header flit faster compared to data flit, as header flit is used for processing the data flits. Existing single error correction and double error detection code is improved and presented in this paper to support faster error correction in header flit with retaining the same number of redundant bits. This improved code is synthesised and results are compared with existing code. The results show that the header flit are decoded faster compared to data flits as the critical path delay is reduced.

As the size of on-chip SRAM caches is increasing rapidly and the physical dimension of the SRAM devices is decreasing, reliability of caches is becoming a growing concern. This is because with increased size of caches, the likelihood of radiation-induced soft faults also increases. As a result, information redundancy in the form of Error Correcting Codes (ECC) is becoming extremely important, especially to protect the larger sized last level caches (LLCs). In typical ECCs, extra redundancy bits are added to every row to detect and correct errors. There is additional encoding (while writing data) and decoding (while reading data) procedures required as well. In caches, these additional area, power and latency overheads need to be minimized as much as possible. To address this problem, we present in this paper Parity++: a novel unequal message protection scheme for last level caches that preferentially provides stronger error protection to certain "special messages". This protection scheme provides Single Error Detection (SED) for all messages and Single Error Correction (SEC) for a subset of messages. Thus, it is stronger than just a basic SED parity and has much lower parity storage overhead (4X lower for a 64-bit memory) and lower error detection energy than a traditional Single Error Correcting, Double Error Detecting (SECDED) code. We also evaluate Parity++ with a memory speculation procedure that can be used with any ECC scheme to hide the decoding latency while reading messages when there are no errors.