Noise in Solid State Devices

Contrarily to current theories based on hypothetical traps where charge carriers can translocate to, this paper gives an explanation for 1/f electrical noise in solid-state devices based on well known electrical effects taking place in these devices. A parasitic capacitor and the backgating effect of its thermal noise, both overlooked in the course of the years, are the basis of the above explanation. The above effect produces a resistance noise with a Lorentzian spectrum in any unbiased resistor. As soon as the resistor is biased, this spectrum is scattered into a continuous set of Lorentzian noise terms that synthesize 1/f noise over a frequency band that is an exponential function of the bias voltage V_DS expressed in thermal units V_T. This is due to the exponential dependence of the dynamical resistance in most semiconductor junctions. A V_DS=180mV is thus enough to give 1/f noise over three decades at room temperature. This unexpected and non-linear feature, where the spectrum of this noise results from the own bias used to measure it, has kept 1/f noise as a puzzling and enigmatic noise for more than eighty years. The above theory, born in the solid-state field, can also be generalized to other devices where two orthogonal forces or energy gradients appear while electrical noise is being measured.

Chapter 7 - Solid State Voltage Amplifiers

We have developed a new simulation methodology for predicting shot noise intensity in Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). In our approach, shot noise in MOSFETs is calculated by employing a two dimensional device simulator in conjunction with the shot noise model of a p-n junction. The accuracy of the noise model has been demonstrated by comparing simulation results with measured noise data of p-n diodes. The intensity of shot noise in various n-MOSFET devices under various bias conditions was estimated beyond GHz operational frequency by using our simulation scheme. At DC or low-frequency region, sub-threshold current dominates the intensity of shot noise. Therefore, shot noise is independent on frequency in this region, and its intensity is exponentially depends on V G , proportional to L -1 , and almost independent on V D . At high-frequency region above GHz frequency, on the other hand, shot noise intensity depends on frequency and is much larger than that of low-frequency region. In particular, the intensity of the RF shot noise is almost independent on L, V D and V G . This suggests that high-frequency shot noise intensity of MOSFETs is decided only by the conditions of source-bulk junction.

formula omitted] Fourth international conference on “Physical aspects of noise in solid state devices”

This Special Section is on 'Noise in devices and circuits' and contains expanded versions of a number of articles that were presented at the SPIE Fluctuations and Noise Symposium - Noise in Devices and Circuits, Santa Fe, New Mexico in June 2003 and were published in Proceedings of the SPIE, volume 5113. The papers in the Special Section are in the broad area of noise in devices and circuits and cover fundamental as well as applied aspects of noise in a variety of semiconductor devices. They are representative of the range of studies in noise from different groups around the world. This Special Section contains papers in silicon diodes, MOS and bipolar transistors, silicon germanium and compound semiconductor transistors, bulk and SOI MOS transistors, polymer transistors, low frequency noise and jitter in electronic oscillators, and the impact of scaling on noise in silicon devices. It covers theory, technology and practical aspects of noise in electronic devices and circuits and will be useful to experts as well as new researchers in the noise field.

We begin this chapter with a discussion of avalanche breakdown and blocking voltage in power devices, which leads naturally into a survey of edge termination techniques. We then discuss the optimum design of unipolar drift regions in devices such as Schottky diodes, JFETs (junction field-effect transistors), and MOSFETs (metal-oxide-semiconductor field effect transistors), with a brief discussion of lateral RESURF (reduced-surface-field) devices. Finally, we present a consistent methodology for optimizing and comparing unipolar and bipolar devices for a particular set of specifications (i.e., blocking voltage and switching frequency).

<div class="htmlview paragraph">A fundamental knowledge of solid-state physics is used to gain understanding of the two basic active solidstate devices-bipolar and field-effect transistors. The bipolar transistor is treated as two junctions communicating through a common region (the base). The functions of charge injection and collection are studied and developed to explain the observed static (d-c) volt-ampere characteristics. Major bipolar-transistor parameters are then reviewed. Finally, the limitations in gain, voltage, and power are discussed. There are basically two forms of field-effect transistors: the junction field effect transistor (JFET) and the metal oxide semiconductor (MOS). Both forms use a voltage applied to a gate electrode or region to control charge (current) flow between source and drain terminals. This action is studied and used to to develop the observed state (d-c) volt-ampere characteristic. The major field-effect transistor parameters are then reviewed. Finally, the limitations in gain, voltage, and power are discussed. Included in the appendixes is a brief review of transistor evolution, which serves as an introduction to device processing information, and an introduction to some of the lesser known solid-state devices. A third appendix explains thermal resistance.</div>

Power electronic devices are crucial components of power converter systems. The evolution of power devices drives the development of power converters, including improvements in performance, reliability, and power capacity. In this chapter, the author expounds the structure, working principle, and static and dynamic characteristics of the conventional PN junction diode. And the silicon carbide (SiC) Schottky barrier diode (SBD), junction barrier Schottky (JBS) diode, trench JBS (T-JBS) diode, and sidewall-enhanced trench JBS (SET-JBS) diode are also discussed and compared. Also, the structures and properties of the gallium oxide (Ga2O3) SBD and heterojunction diode are also summarized. Next, the author gives a detailed analysis and discussion of the silicon power metal-oxide-semiconductor field-effect transistor (MOSFET), superjunction MOSFET, and the SiC MOSFET and JFET, and the Ga2O3 MOSFET. Then, the device structure and operating principle, switching characteristics, and current tailing mechanism of the insulated gate bipolar transistor (IGBT) are also analyzed and summarized in detail. Finally, the energy band structure, working principle, and switching characteristic of the gallium nitride (GaN) high-electron mobility transistor (HEMT), one of the hot devices in the current market, are also described. Finally, the summary and prospect of power electronic devices are also presented in this chapter.

In this paper a new approach of obtaining the electrical properties of the power lateral double-diffused metal-oxide-semiconductor field-effect transistors (LDMOSFET) is proposed. The device is regarded as a junction field-effect transistor (JFET), the N-well region, in series with an active metal-oxide-semiconductor field-effect transistors (MOSFET). The I-V relation of these two parasitic FETs were first separately obtained from actual device structure and then combined together to generate the I-V relation for the power MOSFET. This model also explains why the transconductance has a maximum value at mediate gate voltage and decreases drastically with higher gate voltages. The simulation program, MEDICI, verifies the accuracy of this analytical method. Since the model contains only two parasitic devices, it affords a fast and easy method to analyze the I-V characteristic of power MOSFET.

Scaling of semiconductor devices has pushed CMOS devices close to fundamental limits. The remarkable success story of Moore's law during the last 40 years, predicting the evolution of electronic device performances related to miniaturization, has always been respected. However, electron device challenges are now much more complex. In order to keep Moore's law living, device scaling-down is not enough. So called material and geometry technology boosters have been introduced. High-k dielectrics, silicon-on-insulator substrates or strained silicon are some booster examples, used at sub-micron scale. This work proposes an investigation of a hybrid CMOS/SET technology, based on gate-all-around silicon nanowires. It is shown that a silicon nanowire can serve two device purposes: first as innovative 3D metal-oxide-semiconductor field effect transistor (MOSFET), and second as single electron transistor (SET). The SET is a solid-state electronic device, which controls the transport of a unique or a few electrons. SET functions are not limited by its nano-scaled structure. The smaller is the better. SET consists of a small conductive quantum dot, called island, connected to two reservoirs acting as drain and source by tunnel junctions. The size of the island should be as small as possible – typical values ranging from 1 to 4nm – in order to have room temperature operation. Electron transport from source to island, and from island to drain is controlled by a capacitively coupled gate. The nano-scale size of the island makes the carrier electrostatic repulsion efficient. This effect is called Coulomb Blockade. SET advantages are an ultra-reduced size and a very low power consumption, while SET challenges are variability related to dimension control and background charge effect, room temperature operation and a reduced fan-out. The first chapter of this thesis introduces ideas of up-to-date MOS and SET devices and shows how to combine MOS and SET to obtain original electronic functions. The second chapter is a discussion of the nanowire as a technology platform for the integration of SET devices and also presents TCAD simulation results. Key contributions are reported in chapter three. This is the original and complete description of the different top-down processes used for the integration of a gate-all-around MOS/SET platform. Samples integrated at the EPFL Center of Microtechnology (CMI) are presented. Different approaches have been studied and used in order to overcome lithographic limitations, and to have a fast and reliable integration at moderate cost. This includes auto-aligned techniques, focused ion beam prototyping, and top-down local-SOI and true-SOI nanowires. The local-SOI technique based on silicon nano-channel wires has given the best results and offers a lot of flexibility in term of wire cross-sections and shapes. Gate-all-around silicon nanowires, obtained by sacrificial etching and self-limited oxidation, with a circular 5nm diameter cross-section have been characterized. Chapter four is the validation by measurements of both SET and MOS devices. Excellent room temperature characteristics have been observed in MOS structures, while both ID-VG Coulomb oscillations and ID-VD Coulomb gap are observed on smaller structures at cryogenic temperature (T<20K). The process described has many advantages in comparison with bottom-up grown wires, such an excellent crystallinity of the channel and ohmic source-drain contacts. Finite elements simulations have also highlighted the influence of carrier mobility, channel length and cross-section shape in our defined nanowire structures. The last chapter of this report concludes this work and gives perspectives on the near future. The hybrid combination of silicon nanowire MOSFET and SET can definitely be an appealing approach in order to bridge the gap between emerging nanoelectronic devices and more traditional CMOS.

This research investigates the electro-thermal switching characteristics and lattice temperature profile of a two dimensional (2D) silicon carbide (4H-SiC polytype) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) cell under resistive switching using Silvaco ATLAS Technology Computer Aided Design (TCAD) physics based simulation software. Physics based models were included to account for recombination effects, bandgap narrowing, low field and high field mobility and lattice heating. The electro-thermal simulation was performed at an ambient lattice temperature of 300K. The device was simulated for 100 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 1000 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> drain current densities using a 1 kHz 50% duty cycle gate signal consisting of two cycles and 1.6 kHz 80% duty cycle signal consisting of three cycles. The analysis of lattice temperature profile revealed the formation of thermal hot spots in the vicinity of the (Junction Field Effect Transistor) JFET region in the DMOSFET structure during the switching phase and at the edge of the channel during the conduction phase. The magnitude of temperature rise was dependent on the drain current density used during the simulation.

A Si/SiC hybrid switch is an innovative power semiconductor switch realized by paralleling a Si insulated-gate bipolar transistor (IGBT) and a SiC device (metal-oxide semiconductor field-effect transistor ( mosfet ) or junction field-effect transistor). The Si/SiC hybrid switch combines advantages of Si IGBT's high conduction capability and SiC device's fast switching speed, and effectively addresses Si IGBT's high turn- off loss issue and SiC mosfet 's high cost concern. However, to control the hybrid switch, two separate gate drivers are usually needed, which increases the complexity and cost. In this letter, a simple and effective gate driver circuit is designed for the Si/SiC hybrid switch, which requires only one control signal and gate driver circuit to drive both Si IGBT and the SiC device, making the hybrid switch a typically three-terminal device. The operation principles and design guidelines are presented and analyzed. A three-terminal 1200-V, 200-A hybrid switch prototype in a half-bridge configuration is developed and experimental results verify its effectiveness.

For their function junction field effect transistors (JFETs) depend on reverse-biased junction depletion regions that control majority carrier conduction in thin channels between ohmic contacts to source and drain regions. The structures require fewer masking steps and fewer diffusions than bipolar transistors and may be made either n channel or p channel. The contact through which the majority carriers enter the channel is termed the source S, and the exit is the drain D. The circuit symbol and some characteristics for an n channel FET are shown in Fig. 6.1. A MESFET is similar except that the junction is a metal-semiconductor barrier. MOSFETs (metal-oxide-semiconductor FETs) are considered in Chap. 7.

This work provides a way to reduce the parasitic effect that is present in ordinary power MOSFETs. In this device, source and drain doping is eliminated from the design process using charge plasma technique leading to the reduction of parasitic effects due to parasitic bipolar junction transistor (BJT) from the device. A vertical metal oxide-semiconductor field effect transistor (VMOS) is proposed by employing this technique. It is simulated and compared with the conventional vertical double diffused metal-oxide-semiconductor field effect transistor (VDMOS). In this work, the proposed VMOS is also tested with various materials that can be used for plasma formation. When compared to the conventional VDMOS, the proposed VMOS exhibits 54.21% increment in breakdown voltage, 55.03% reduction in ON-resistance and approximately two times of the drain current density.

With the development of down-scaling of CMOS technology for low power, mixed-signal, and high frequency applications, the optimal high frequency performance is shown to be shifted from lower moderate inversion toward weak inversion regimes. High-frequency noise model is a prerequisite for designing the radio frequency and millimeter-wave circuits, and is essential for the noise analysis of nanoscale metal-oxide-semiconductor field-effect transistors (MOSFETs). In this paper, based on the physical structure of 40 nm MOSFET and by considering the drift-diffusion equation and charge conservation law, accurate physics-based unified high-frequency noise model is developed for induced gatecurrent noise and its cross-correlation with drain-current noise under different bias conditions, which is used to describe the frequency and bias dependence of 40 nm MOSFET from weak inversion to strong inversion regime. Especially, the effective gate overdrive is explicitly included in unified noise model to offer excellent accuracy, continuity and smoothness, and this makes the proposed analytical models convenient to directly reflect the relationship between the noise model and bias condition. Besides, new analytical model is derived for the induced-gate current noise and its cross-correlation term of weakly inverted MOSFET. These simple expressions not only serve as the asymptotic limit for the validation of the proposed physics-based unified model, but also provide a clearer insight into and better understanding of the gate noise behavior and their cross-correlation in the weak-inversion region. Moreover, in terms of the proposed subthreshold noise model, the charge of weak inversion rather than the normal effective channel thickness approximation is involved. In this way, the model accuracy can be improved. Furthermore, a detailed derivation and discussion are presented by analyzing the physics-based noise generation mechanism of transistor including the channel thermal noise and the shot noise based on the small-signal equivalent circuit of the 40 nm MOSFET device. Using these expressions it is possible to extract the values of all the noise model parameters directly from measurement. The proposed model is demonstrated by using noise data from both measurement and the noise simulation. Excellent agreement between simulated and measured noise data shows that the proposed model can be used for predicting the noise behavior of 40 nm MOSFET under different dimensions and operating conditions. The applicability of reported model for drain-current noise is also verified. As far as small-signal (i.e., linear) bias-dependent operation is concerned, it is shown how most of the findings of this work can also be used to predict the data of long channel devices in the strong-inversion regimes.