Novel First‐Order Current‐Mode All‐Pass Sections Using CCIII

In the field of analog VLSI design, current conveyors have reasonably established their identity as an important circuit design element. In the literature published during the past few years, numerous application have been reported which are based on a variety of current conveyors. In this paper, an oscillator circuit has been proposed. This oscillator is designed using a single positive type second generation current controlled current conveyor (CCCII+). A CCCII has parasitic input resistance on it’s current input node. This resistance could be exploited to reduce circuit complexities. Thus in this accord, a novel oscillator circuit is proposed which utilizes the parasitic resistance of the CCCII+ along with a few more passive components.

A current op amp with a differential output and a single-ended input can be configured from a single second generation current conveyor and an output stage with a differential floating current source. Owing to a very simple basic configuration with a single dominant pole, this design combines a high bandwidth with a high open loop gain. In this paper we present the basic configuration, derive the fundamental equations for the performance of the op amp, and describe some design considerations with respect to an optimization of the op amp for a high bandwidth. Simulation results are given from a commercially available 2µm CMOS process resulting in an open loop differential gain of 94dB and a gain-bandwidth product of 128M H z at a supply voltage of 3V and a supply current of 25µA. The design has been experimentally verified through a test circuit and experimental results from this confirm the expected behaviour.

A new single-element-controlled sinusoidal oscillator circuit that incorporates two second generation current conveyors (CCIIs), two grounded capacitors and two resistors is presented and analysed. The circuit is beneficial to monolithic integrated circuit implementation by the use of grounded capacitors. In addition, a new current-controlled sinusoidal oscillator using only two second generation current controlled conveyors (CCCIIs) and two grounded capacitors can be achieved by replacing CCIIs and resistors series at X terminals with CCCIIs. The oscillators provide extremely low passive ω0-sensitivities and good frequency stability. Moreover, the oscillation frequencies of the CCII-based and the CCCII-based oscillators can be controlled, respectively, by a grounded resistor and by an external bias current. Experimental and SPICE simulation results that confirm the theoretical predictions are given.

This paper presents two new single-resistance-controlled-oscillators (SRCOs), that employ a single first-generation current conveyor (CC) along with one/two voltage buffer(s) and a minimum of (five) passive components. Apart from providing noninteractive controls for both frequency of oscillation and condition of oscillation, a novel feature of these circuits is that they provide voltage-mode as well as currentmode outputs explicitly from the same structures, which is not available in any of the single-CC-based SRCOs published previously.

In this article, developments of Second Generation Current Conveyors (CCII) that are realized by based on the use of a differential amplifier (diff-amp) as a circuit building block are reviewed. The basic concepts of current conveyor are firstly outlined. One of the first CMOS-based promising techniques to implement CCII that proposed by Surakampontorn et al. is reviewed [9-11]. The applications of Surakampontorn’s CCII as basic circuit building blocks to realize analog circuits and systems and the modifications methods to provide multiple outputs CCIIs are outlined and discussed. Based on feedback mechanisms, diff-amp-based CCIIs that are designed by modified from the CCII are also outlined and discussed. In order to understand the improvement, the characteristics of the CCIIs that have been compared through simulation results by Hassanenin et al. [11] are presented. Finally, the concept of chemical current conveyor (CCCII) is also noted.

Reply to "Comments by A. M. Soliman on 'realization of an all-pass transfer function using the second generation current conveyor'"

Two new types of floating current conveyors are introduced. Each type has four ports: Y, X and two Z ports. The first type is the Floating Second Generation Current Conveyor (FCCII) and includes both CCII+ and CCII- as special cases. The second type is the Floating Inverting Second Generation Current Conveyor (FICCII) and includes both ICCII+ and ICCII- as special cases. The Nodal Admittance Matrix (NAM) stamp for the Nullator-Pathological Current Mirror is derived. Examples are given together with a CMOS circuit realizing both the FCCII and FICCII.

Recently, it has been shown by Paul-Dey-Patranabis that a floating NIC can be realized with two second generation current conveyors (CC), without constraints. In this communication it is shown that more useful floating generalized positive immittance converter/inverter elements too can be realized with only two second generation current conveyors.

This brief paper deals with using the particle swarm optimization metaheuristic for optimally sizing CMOS positive second generation current conveyors (CCII+). Both static and dynamic performances are improved. Pareto front is generated while minimizing parasitic X-port input resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</sub> and maximizing current high cut off frequency f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ci</sub> . The translinear implementation in CMOS technology is presented. Boundaries of the generated Pareto boarder are 400Ω and 2GHz for R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</sub> and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ci</sub> respectively. SPICE simulation results are presented to validate obtained sizing.

The realisation of a differential input current mode integrator network using the second generation current conveyor (CC II) is proposed. Even with nonideal CC IIs, true differential input capability and precise compensation of the time constant tau can be obtained by suitable design. A minimum of passive RC components is needed; their interchanged connection yields alternate differentiator functions. >

A new CMOS dual-X second generation current conveyor (DXCCII) with an FDNR circuit application

Evolutionary algorithms have been shown to be well adapted to solve multi-objective optimization problems. In this paper, two of them, will be applied to optimize the classical circuit of second generation current conveyor(CCII+). The optimization is performed in the framework of 0.181μm technology, and results are integrated in Cadence Virtuoso simulation tool to show the validity of the obtained results. Final design characteristics obtained by the two technics are in agreement and are better than the previously reported results in literature.

This paper aims to introduce a novel Fully Differential second generation Current Conveyor (FDCCII) and its application to design a novel Low Power (LP), very high CMRR, and wide bandwidth (BW) Current Mode Instrumentation Amplifier (CMIA). In the proposed application, CMRR, as the most important feature, has been greatly improved by using both common mode feed forward (CMFF) and common mode feedback (CMFB) techniques, which are verified by a perfect circuit analysis. As another unique quality, it neither needs well-matched active blocks nor matched resistors but inherently improves CMRR, BW, and power consumption hence gains an excellent matchless choice for integration. The FDCCII has been designed using 0.18 um TSMC CMOS Technology with ±1.2 V supply voltages. The simulation of the proposed FDCCII and CMIA have been done in HSPICE LEVEL 49. Simulation results for the proposed CMIA are as follow: Voltage CMRR of 216 dB, voltage CMRR BW of 300 Hz. Intrinsic resistance of X-terminals is only 45 Ω and the power dissipation is 383.4 μW. Most favourably, it shows a constant differential voltage gain BW of 18.1 MHz for variable gains (here ranging from 0 dB to 45.7 dB for example) removing the bottleneck of constant gain-BW product of Voltage mode circuits.

Two new CMOS realization circuits of current-controlled second generation current conveyor (CMOS CCCII) based on compound MOS translinear loop and MOS current mirrors is proposed. The circuit can satisfy port characteristic without need for restriction conditions which relate to fabrication parameters, so the difficulties of design and fabrication can be decreased. It presents such advantages as easy realization in the fabrication, simple circuit configuration, wide bandwidth, low power consumption and so on. The principle of the circuit is analyzed in detail. PSPICE simulation results for the proposed circuit in 0.5 mum CMOS technology is included. In the frequency range of 0~20 MHz, the simulation results show the proposed circuit meet ideal port characteristic of CCCII.

The design of low power and low voltage analog circuits is truly challenging. Therefore different approaches have been proposed and successfully employed. In this paper some of the low voltage topologies like Bulk Driven, Self-Cascode and DTMOS have been presented, and issues related to design are discussed briefly. These topologies are also used to design second generation current conveyors (CCII) and voltage mplifiers. The CCII is an important building block of a current feedback circuit like a current feedback operational amplifier (CFOA). Low voltage and low power are needed when those circuits are employed in the biomedical application and portable equipment. The designs are implemented using 0.18 µm CMOS technology.