Numerical Linear Algebra, Digital Signal Processing and Parallel Algorithms

A fundamental mathematical field with many applications in science and engineering is linear algebra. This paper investigates the various applications of linear algebra in the fields of traffic flow analysis, electric circuits, cubic spline interpolation, and genetics. This research delves into individual applications while emphasizing cross-disciplinary insights, fostering innovative solutions through the convergence of genetics, cubic spline interpolation, circuits, and traffic flow analysis. The research employs specific methodologies in each application area to demonstrate the practical integration of linear algebra in genetics, cubic spline interpolation, electric circuits, and traffic flow analysis. In genetics, linear algebra techniques are utilized to represent genetic data using matrices, analyze genotype distributions across generations, and identify genotype-phenotype associations. For cubic spline interpolation, linear algebra is employed to construct smooth interpolating curves, involving the derivation of equations for spline functions and the determination of coefficients using boundary conditions and continuity requirements. In electric circuit analysis, linear algebra is crucial for modeling circuit elements, formulating systems of linear equations based on Kirchhoff's laws, and solving for voltage and current distributions in circuits. In traffic flow analysis, linear algebra techniques are used to represent traffic movement in networks, formulate systems of linear equations representing traffic flow dynamics, and solve for traffic flow solutions to optimize transportation networks. By addressing contemporary challenges, emerging research frontiers, and future trajectories at the intersection of linear algebra and diverse domains, this study underscores the profound impact of mathematical tools in advancing understanding and resolving complex real-world problems across multiple fields.

NATO advanced study institute “an interdisciplinary meeting on numerical linear algebra, digital signal processing and parallel algorithms”: 1–12 August 1988, Leuven, Belgium

This paper presents an algebraic theory of linear signal processing. At the core of algebraic signal processing is the concept of a linear signal model defined as a triple (A, M, phi), where familiar concepts like the filter space and the signal space are cast as an algebra A and a module M, respectively, and phi generalizes the concept of the z-transform to bijective linear mappings from a vector space of, e.g., signal samples, into the module M. A signal model provides the structure for a particular linear signal processing application, such as infinite and finite discrete time, or infinite or finite discrete space, or the various forms of multidimensional linear signal processing. As soon as a signal model is chosen, basic ingredients follow, including the associated notions of filtering, spectrum, and Fourier transform. The shift operator is a key concept in the algebraic theory: it is the generator of the algebra of filters A. Once the shift is chosen, a well-defined methodology leads to the associated signal model. Different shifts correspond to infinite and finite time models with associated infinite and finite z-transforms, and to infinite and finite space models with associated infinite and finite C-transforms (that we introduce). In particular, we show that the 16 discrete cosine and sine transforms are Fourier transforms for the finite space models. Other definitions of the shift naturally lead to new signal models and to new transforms as associated Fourier transforms in one and higher dimensions, separable and non-separable. We explain in algebraic terms shift-invariance (the algebra of filters A is commutative), the role of boundary conditions and signal extensions, the connections between linear transforms and linear finite Gauss-Markov fields, and several other concepts and connections.

During the 1930s and 1940s Norbert Wiener and others invented the core concepts of linear signal processing. These ideas quickly became popular and played a significant role in the Allies' victory in World War II. During and after the war, linear signal processing theory was greatly expanded and began to take on the character of an imposing monolith. By the mid- 1940s, Wiener (and others, such as Dennis Gabor) came to recognize that linear signal processing theory, while interesting and very useful, was only a piece of a much larger picture. In 1946 and 1958 Gabor and Wiener, respectively, attempted to address the whole picture. While they were not completely successful, they did implicitly set an agenda for a more general approach to signal processing. Although a few others have, from time to time, addressed this agenda; in terms of the signal processing community as a whole it still remains lost in the shadow of the ever-growing monolith of linear signal processing theory. The thesis of this paper is that it is now time to get on with the Wiener and Gabor agenda. It is time to make general signal processing the mainstream focus of the subject. It is argued here that the best way to do this is to abandon the transfer function/Fourier analysis/z-transform approach of the current linear signal processing regime and replace it with a much more natural intellectual framework for general signal processing--the framework offered by neurocomputing. A potential benefit of this refocusing of the field is that the detailed engineering might soon be left to machines, while human technologists will be able to concentrate on the art of signal sculpting.© (1991) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

This paper presents some OpenCL implementations for Cholesky decomposition, a very popular algorithm used in linear algebra and signal processing applications. The Cholesky algorithm represents a very interesting candidate for OpenCL implementation since it contains sequential parts besides parallel ones. Furthermore, one step involves just a small amount of calculations. These characteristics pose challenges which call for suitable techniques to overcome the limitations of the language. We propose several versions of the implementation of the Cholesky algorithm, then provide an analysis of the trade off between complexity and performance offered by each of them. We also analyze the differences between execution of the program on GPU and on multicore CPU.

The design and analysis of software which implements digital signal processing (DSP) algorithms on multiprocessor systems is examined. The DSP algorithms that are considered exhibit certain characteristics which are common of DSP algorithms used in communication and control systems. The analysis methods developed use linear complexity algorithms to analyze the software that implements the DSP algorithms. The first step involves finding the repeat factors associated with a basic cycle of the algorithm. Using these repeat factors it is straightforward to (1) find the precedence relationships between tasks and finally a feasible schedule for the multiprocessor, and (2) coordinate and organize the efforts to optimize the software. >

Validation of Peripheral Pulse Wave Analysis Technique to Detect Aortic Valve State in Continuous-Flow LVADs1

Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate(MAC) and inner product are among some of the frequently used computation Intensive Arithmetic Functions(CIAF) currently implemented in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors m its arithmetic and logic unit. Since multiplication dominates the execution tune of most DSP algorithms, so there is a need of high speed multiplier. Currently, multiplication time is still the dominant factor in determining the instruction cycle time of a DSP chip. The demand for high speed processing has been increasing as a result of expanding computer and signal processing applications. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications . One of the key arithmetic operations in such applications is multiplication and the development of fast multiplier circuit has been a subject of interest over decades. Multiplier based on Vedic Mathematics is one of the fast and low power multiplier. Employing this technique in the computation algorithms will reduce the complexity, execution time, power etc. This vedic based multiplier is compared with binary multiplier(partial products method).

Traditional digital signal processing technology based on DSP and FPGA is more suitable for real-time signal processing, and is limited by data scale and frequency resolution, making it unsuitable for offline data processing, analysis and mining under large-scale data Application. At present, the industrial big data analysis platform can use Spark as a calculation engine for real-time signal processing and offline signal processing acceleration, but the analysis platform lacks mathematical calculation solutions such as digital signal processing suitable for distributed parallel calculation engines. This article is based on time the parity decomposition is selected, and the fast Fourier transform is realized by MATLAB software. Based on an example of the application of the compiled FFT source program, this article analyses the frequency spectrum of discrete-time and continuous-time signals of limited length.

Digital signal processing (DSP) has been widely applied in optical communication systems to mitigate various signal distortions and has become one of the key technologies that have sustained data traffic growth over the past decade. However, the strict energy budget of application-specific integrated circuit-based DSP chips has prevented the deployment of some powerful but computationally costly DSP algorithms in real applications. As a result, fiber nonlinearity-induced signal distortions impede fiber communication systems, especially in wavelength-division multiplexed (WDM) transmission systems. To solve these challenges in DSP, there has been a surge of interest in implementing neural networks-based signal processing using photonics hardware (i.e., photonic neural networks). Photonic neural networks promise to break performance limitations in electronics and gain advantages in bandwidth, latency, and power consumption in solving intellectual tasks that are unreachable by conventional digital electronic platforms. This work proposes a photonic recurrent neural network (RNN) capable of simultaneously resolving dispersion and both intra and inter-channel fiber nonlinearities in multiple WDM channels in the photonic domain, for the first time to our best knowledge. Furthermore, our photonic RNN can directly process optical WDM signals in the photonic domain, avoiding prohibitive energy consumption and speed overhead in analog to digital converters (ADCs). Our proposed photonic RNN is fully compatible with mature silicon photonic fabrications. We demonstrate in simulation that our photonic RNN can process multiple WDM channels simultaneously and achieve a reduced bit error rate compared to typical DSP algorithms for all WDM channels in a pulse-amplitude modulation 4-level (PAM4) transmission system, thanks to its unique capability to address inter-channel fiber nonlinearities. In addition to signal quality performance, the proposed system also promises to significantly reduce the power consumption and the latency compared to the state-of-the-art DSP chips, according to our power and latency analysis.

The possibility to use CRLH (Composite Right/Left-Handed) cells to realize both distributed wide-band filters for linear signal processing and non-linear devices like frequency doublers is investigated analytically and numerically. Full-wave electromagnetic simulations are performed for the filtering structure by means of a commercial software package and confirm the validity of the analytic results. Numerical results for CRLH NLTL (Non-Linear Transmission Line) obtained by using the Microwave Office are discussed, providing design considerations about the synthesis of such a component.

Background. Far-Field R-Wave (FFRW) oversensing and P wave blanking are the major causes of inaccurate atrial signal classification in current pacemaker (PM) devices leading to inaccurate stored diagnostic information and to inadequate PM reactions like mode-switching or preventive pacing. The prospective and multi-center MARS (Morphology of Atrial Signals) study therefore investigated during daily life the capabilities of Digital Signal Processing (DSP) in an implanted dual chamber PM to improve P-wave classification accuracy. Methods . 55 patients with an implanted dual chamber PM (Vitatron T- or C-series) were included: During 24 hours with daily life activity and a stress test, a Holter ECG collected surface ECG, PM markers and all atrial EGM’s. The DSP algorithm analysed atrial events sensed nearby a ventricular event using the minimum and the maximum amplitude of the digitalized and filtered signal and the maximum and minimum amplitude of the slope signal. After comparing to the characteristics of a normal P wave, each of these atrial signals were then classified as a true atrial signal or FFRW. DSP classification results were then compared to the conventional PM signal classification by three independent reviewers. Results . Classification accuracy for the traditional PM functionality after optimizing blanking and sensitivity settings was 97.1% (19.5–100%) as compared to 99.4% (76.9–100%) using the DSP algorithm (p<0.001). Conclusion . The DSP algorithm significantly improved the classification accuracy of sensed atrial events as an important prerequisite for a correct diagnostic and therapeutic PM function. The herewith presented approach of analysing atrial signals by form and timing may allow to reduce or even eliminate atrial blanking periods thus leading to larger PM sensing windows to prevent from atrial tachyarrhythmia undersensing without an increase in FFRW sensing.

Scientific and engineering research is becoming increasingly dependent upon the development and implementation of efficient parallel algorithms on modern high-performance computers. Numerical linear algebra is an indispensable tool in such research and this paper attempts to collect and describe a selection of some of its more important parallel algorithms. The purpose is to review the current status and to provide an overall perspective of parallel algorithms for solving dense, banded, or block-structured problems arising in the major areas of direct solution of linear systems, least squares computations, eigenvalue and singular value computations, and rapid elliptic solvers. A major emphasis is given here to certain computational primitives whose efficient execution on parallel and vector computers is essential in order to obtain high performance algorithms.

The KASSPER project is a Defense Advanced Research Projects Agency (DARPA) program which has the goal of improving the performance of ground moving target indicator (GMTI) radar systems by incorporating external sources of knowledge into the signal processing chain. The KASSPER real-time signal processing architecture is a radar system scheduling and signal processing framework that is being developed at Massachusetts Institute of Technology Lincoln Laboratory (MIT LL). This paper discusses the design of the architecture, knowledge handling issues. resource scheduling issues, the current state of the prototype implementation of the framework, and the current state of the project's real-time processor testbed.

Enhancements to array processors in the form of broadcast buses have been proposed for improving the speeds of algorithms in linear algebra, image processing and computational geometry. In this paper, we consider certain practical issues in such arrays which include fewer processors connected to the broadcast buses and finite time, namely log N time for broadcasting data to N processors. We propose a modified broadcast bus VLSI architecture which consists of a √N × √N mesh connected structure and a hierarchy of broadcast buses in each row and in each column such that every bus has k PE's. That is, in any row or column, in the first level there are \(\frac{{\sqrt N }}{k}\)buses with groups of k PE's connected to each bus. One PE from each of this group is connected to second level of buses in a similar manner. This is recursively done until there are only k PE's left which are connected by a broadcast bus. With this architecture, maximum, minimum, or sum of N values can be found in O(log N), median row of a binary picture in O(log N), shortest distance between two points in O(log N). This architecture is well suited for parallel processing of applications in Linear Algebra, Image Processing, Computational Geometry and Numerical Computations. These restricted connections to buses reduces the I/O ports significantly, and therefore, is more suitable for VLSI implementation.