Object oriented programming with a limited instruction set

The level of support for high level programming languages (HLPLs), despite the claim of support by some of the newly introduced microprocessors, is inadequate despite the falling (rising) cost of hardware (software). Computer systems that are to be used to run programs written exclusively in HLPLs have a need for a multiprocessor/multiarchitecture microprocessor design (M3D); the personal/desk-top computers are prime examples. The HLPLs that will be used in programming these systems will be grouped according to their structures. Each group of languages will require their own instruction set; the hardware and software needs will determine the type of architecture configuration, i.e. aspects such as: register-to-register, memory-to-memory, stack, or a combination of these. The overall system should be divided up into functional units, e.g. ALU, compiler/translator, etc. Each functional or subfunctional unit will be implemented in software, firmware, hardware, or a combination of these with implementation decision based on the speed criticality, cost, technology, and the need to modify the unit. This approach will lead to a cop-down-design, and will also reduce the semantic gap, software and system cost, and down-time.

RISC

Compilers and interpreters are systems-software programs which are used to implement high-level languages; they facilitate the running of high-level language programs on a particular computer, even though the computer can only directly execute programs written in its own, low-level, machine code. Each compiler, or interpreter, implements only one high-level language, and so a computer system will usually have several of them, so that programs in several different high-level languages can be executed.

This thesis presents research to build and evaluate embedding of a textual form of state machines into high-level programming languages. The work entailed adding state machine syntax and code generation to the Umple model-oriented programming technology. The added concepts include states, transitions, actions, and composite states as found in the Unified Modeling Language (UML). This approach allows software developers to take advantage of the modeling abstractions in their textual environments, without sacrificing the value added of visual modeling. Our efforts in developing state machines in Umple followed a test-driven approach to ensure high quality and usability of the technology. We have also developed a syntax-directed editor for Umple, similar to those available to other high-level programming languages. We conducted a grounded theory study of Umple users and used the findings iteratively to guide our experimental development. Finally, we conducted a controlled experiment to evaluate the effectiveness of our approach. By enhancing the code to be almost as expressive as the model, we further support model-code duality; the notion that both model and code are two faces for the same coin. Systems can be and should be equally-well specified textually and diagrammatically. Such duality will benefit both modelers and coders alike. Our work suggests that code enhanced with state machine modeling abstractions is semantically equivalent to visual state machine models. The flow of the thesis is as follows; the research hypothesis and questions are presented in “Chapter 1: Introduction”. The background is explored in “Chapter 2: Background”. “Chapter 3: Syntax and semantics of simple state machines” and “Chapter 4: Syntax and semantics of composite state machines” investigate simple and composite state machines in Umple, respectively. “Chapter 5: Implementation of composite state machines” presents the approach we adopt for the implementation of composite state machines that avoids explosion of the amount of generated code. From this point on, the thesis presents empirical work. A grounded theory study is presented in “Chapter 6: A Grounded theory study of Umple”, followed by a controlled experiment in “Chapter 7: Experimentation”. These two chapters constitute our validation and evaluation of Umple research. Related and future work is presented in “Chapter 8: Related work”.

To eliminate the conceptual distance between the hardware instruction set and the user interface, some architects advocate High Level Language (HLL) machines. To obtain simple, fast and cheap machines, some architects advocate Reduced Instruction Set Computer (RISC) machines. This paper reconciles both views and presents an architecture which has both an HLL user interface and a RISC hardware. Each instance of this architecture is a module of an HLL multiprocessor system. Functional programming languages offer a bridge between mathematical models of computation and multiprocessor system environments. We choose the language AFPL (A Functional Programming Language) as the HLL user interface. AFPL's direct execution model, based on a tree structured internal representation, takes advantage of the parallelism inherent in programs by decomposing them on the fly into tasks which can be performed concurrently.

The huge processing power needed by multimedia applications has led to multimedia extensions in the instruction set of microprocessors which exploit subword parallelism. Examples of these extended instruction sets are the Visual Instruction Set of the UltraSPARC processor, the AltiVec instruction set of the PowerPC processor, the MMX and ISS extensions of the Pentium processors, and the MAX-2 instruction set of the HP PA-RISC processor. Currently, these extensions can only be used by programs written in assembly language, through system libraries or by calling specialized macros in a high-level language. Therefore, these instructions are not used by most applications. We propose two code generation techniques to produce native code using these multimedia extensions for programs written in a high-level language: classical vectorization and vectorization by unrolling. Vectorization by unrolling is simpler than classical vectorization since data dependence analysis is reduced to acyclic control flow graph analysis. Furthermore, we address the problem of unaligned memory accesses. This can be handled by both static analysis and dynamic runtime checking. Preliminary experimental results for a code generator for the UltraSPARC VIS instruction set show that speedups of up to a factor of 4.8 are possible, and that vectorization by unrolling is much simpler but as effective as classical vectorization.

Most programmers at Texas Instruments feel that writing in a high-level language (HLL) is one effective way to cut costs and that this is particularly true of a language like Pascal, which lends itself to top-down structuring. When our programmers compare writing in Pascal with writing in native microprocessor assembly language, they find that programmer efficiency increases by a factor of 2.5 to 3 and that software development and maintenance time, after the problem has been analyzed, is reduced by a factor of 2. The switch from machine code to Pascal increases productivity for three reasons: Each program high-level statement creates several machine instructions that permit the programmer to solve the problem at an abstract level rather than deal in machine code. A structured HLL like Pascal allows problems to be solved the way the natural thought processes work-from the top down. Because Pascal is easier to read, it is easier to modify.

Conventional instruction sets or directly interpretable languages (DILs) have not been designed with high-level languages (HLLs) in mind. The modern design problem is to derive a space-time efficient DIL for a HLL processing system. In this paper, we present our approach to the problem of designing well-matched, space-time efficient DILs. A systematic, syntax- and semantics-directed DIL design methodology is presented. It calls for an incremental transformation of the source HLL, until a suitable target DIL is obtained. At the heart of the methodology is a canonic set of language transformations. An experimental study, involving several systematically derived DILs is carried out in order to characterize the relative merits and disadvantages of various sequences of transformations. Various space, time and interpretability trade-offs implied by the transformations are studied.

The existing tools of deductive verification allow us to successfully prove the correctness of functions written in high-level languages such as C or Java. However, this may not be enough for critical software because even fully verified code cannot guarantee the correct generation of machine code by the compiler. At the moment, developers of such systems have to accept the compiler correctness assumption, which, however, is extremely undesirable, but inevitable due to the lack of full-fledged systems of formal verification of machine code. It is also worth noting that the verification of machine code by a person directly is an extremely time-consuming task due to the high complexity and large amounts of machine code. One of the approaches to simplify the verification of machine code is automatic deductive verification reusing the formal specification of the high-level language function. The formal specification of the function consists of the specification of the pre- and postcondition, as well as loop invariants, which specify conditions that are satified at each iteration of the loop. When compiling a program into machine code, pre- and postconditions are preserved, which, however, cannot be said about loop invariants. This fact is one of the main problems of automatic verification of machine code with loops. Another important problem is that high-level function variables often have ‘projections' to both registers and memory at the machine code level, and the verification procedure requires that invariants be described for each variable, and therefore the missing invariants must be generated. This paper presents an approach to solving these problems, based on the analysis of the control flow graph, and intelligent search of the locations of variables.

Analog/mixed-signal machine learning (ML) accelerators exploit the unique computing capability of analog/mixed-signal circuits and inherent error tolerance of ML algorithms to obtain higher energy efficiencies than digital ML accelerators. Unfortunately, these analog/mixed-signal ML accelerators lack programmability, and even instruction set interfaces, to support diverse ML algorithms or to enable essential software control over the energy-vs-accuracy tradeoffs. We propose PROMISE, the first end-to-end design of a PROgrammable MIxed-Signal accElerator from Instruction Set Architecture (ISA) to high-level language compiler for acceleration of diverse ML algorithms. We first identify prevalent operations in widely-used ML algorithms and key constraints in supporting these operations for a programmable mixed-signal accelerator. Second, based on that analysis, we propose an ISA with a PROMISE architecture built with silicon-validated components for mixed-signal operations. Third, we develop a compiler that can take a ML algorithm described in a high-level programming language (Julia) and generate PROMISE code, with an IR design that is both language-neutral and abstracts away unnecessary hardware details. Fourth, we show how the compiler can map an application-level error tolerance specification for neural network applications down to low-level hardware parameters (swing voltages for each application Task) to minimize energy consumption. Our experiments show that PROMISE can accelerate diverse ML algorithms with energy efficiency competitive even with fixed-function digital ASICs for specific ML algorithms, and the compiler optimization achieves significant additional energy savings even for only 1% extra errors.

The emerging technology of the System-on-Chip (SoC) is presenting new challenges at both the hardware and software stages of the design process. At present, system software engineers, e.g. high-level programming language (e.g. C/C++) compiler writers for processor cores, are working at the abstraction level of instruction set architecture (ISA) and its compiler optimization. On the other hand, the hardware engineers for the processor cores and other devices are working at a lower level abstraction level, e.g. RTL level, and using hardware description languages (e.g. VHDL, Verilog) and associated silicon compiler tools. Problems of communication gaps between the two world continue to exist due to the different abstraction levels, and the use of different design languages, incompatible tools and fragmented design flow, etc.In this talk, we discuss such gaps with examples illustrating the limits of optimization that can be performed from the hardware/software alone. With the demand of aggressive exploitation of instruction-level parallelism with high-performance uniprocessor core as well as the need of multiprocessor cores - such gaps must be bridged. Such optimization includes instruction scheduling; register allocation, loop scheduling, locality optimization, etc. Such gaps also affect software debugging (including performance debugging) as well as hardware verification.We briefly outline solution challenges and opportunities in this direction.

Software development is a greatly multifaceted and intellect-oriented movement. In the early days of program development, developers engraved programs using machine language in which programmers consumed added time, thinking about a particular machine’s instruction set than the difficulty at hand. Progressively, programmers wandered to higher level languages. In order to progress software using higher level languages, there are different approaches and selection of software development approach depending on the type of application to be established. Aspect-oriented software development (AOSD) is a novel paradigm in software development that addresses certain concerns in software development that regards modularization as an important aspect. The practices of AOSD create the possibilities to modularize, crosscutting the concerns of a system. Analogous to objects in object-oriented software development, aspects in AOSD may ascend at any point of time of the software life cycle, containing requirements specification, design, implementation, etc. As this effort is built on empirical validating aspect-oriented metrics, coupling on method call (CMC) metric is selected. This work focuses on empirical validation of the metrics. Novel metric is cognitive weighted metric, which is calculated for CMC to calculate the coupling complexity value of the aspect.

Incorporating user-oriented features usually found only in much larger computers, the first models of the Eclipse line, the $100 and $200, use a high speed micro-programmed central processor, and can run with either; core or semiconductor memories, or both. The core and semiconductor memories are available with an error detection and correction feature that can find and correct; single bit errors caused by the computer. The semiconductor memories use a high-speed cache to increase memory speed. The Eclipse $100, the smaller of the two computers, will be used by oems or by end users who need a smaller system to meet their requirements. The Eclipse $100 is 5-1/4 inches high, and holds six standard Data General printed circuit boards. It costs $9200, with 16k bytes of core memory, and $10,700 with 16k bytes of semiconductor memory. Eclipse $100 deliveries will begin in December. The Eclipse $200, a system-oriented computer that can hold 16 printed circuit boards, will be used by system builders or end users who will build large scale computing systems around it. The Eclipse $200 is 10-1/2 inches high, and costs $16,300 with 32k bytes of core memory, and $19,300 with 32k bytes of semiconductor memory. Deliveries of the Eclipse $200 will begin in February. The instruction set of both Eclipse computers is microprogrammed in the central processor. There are over 40 new instruction in the Eclipse computers. Programs written on Nova computers will run on either the Eclipse $100 or $200. The central processor includes a Writeable Control Store making up to 256, 56-bit words available to write specialized micro-programmed instructions. The instruction set is enhanced to help programmers writing in assembly language or high-level language programs. Hardware memory stacks, supported by comprehensive instructions, make programming more efficient, while block, word, byte and bit manipulation instructions improve system performance. Instructions are both single word and double word instructions.

Decompilation plays a critical role in firmware analysis and reverse engineering by enabling the recovery of high-level source code from binary executables. However, existing neural decompilation models often face challenges due to the semantic gap between assembly code and high-level languages, and they typically require large-scale models that impose significant computational demands. In this paper, we propose DECodeT5, a lightweight and efficient neural decompilation method for the C language. DECodeT5 builds upon the CodeT5 code generation model by integrating a pre-trained assembly encoder in place of its original embedding layer. This modification allows for more effective semantic learning from assembly code, improving the model’s ability to capture the intricacies of assembly-to-source code mapping. The architecture of DECodeT5 not only accelerates convergence during end-to-end decompilation tasks but also supports rapid adaptation across different compilers and instruction set architectures (ISAs) by swapping out the encoder module as needed. Our experimental evaluation on the HumanEval and Exebench benchmarks reveals that DECodeT5 significantly improves semantic recovery accuracy, outperforming Ghidra by over 83% and LLM4Decompile by more than 43% in terms of execution recovery. Furthermore, DECodeT5 maintains a compact model size of only 360M parameters, providing inference speeds that are twice as fast as LLM4Decompile. These results underscore DECodeT5’s suitability for deployment in resource-constrained environments and its flexibility in adapting to real-world reverse engineering scenarios, offering a practical solution for modern firmware analysis and security tasks.

A path object is a set of instructions plus the values of associated parameters that would be used by an aircraft’s flight management system (FMS) or area navigation (RNAV) computer to construct a flight trajectory on the basis of the values of the parameters provided by the pilot or air traffic control (ATC) system. The concept of path objects and its applicability for development of FMS- or RNAV-based flight paths for aircraft routes are described. The use of path objects requires only a small number of parameters for specification of an RNAV route, and the computer then calculates the resulting flight path. Because most RNAV routes are just variations of the same basic shapes, many RNAV routes can be generated from a single path object by changing just one or two parameters. This offers the capability to reduce the size of the navigation database by a significant amount. This also allows the dynamic alteration of three-dimensional FMS-RNAV routes instead of radar vectoring, which represents a significant improvement in ATC procedures. Because of the compact expressions for the path objects, these procedures could be used in a voice communications environment as well as a data link environment. A path object can be thought of as a high-level language with which aircraft and ATC systems communicate flight path intentions. The concept of FMS- or RNAV-stored path objects is a change in thinking about the role of avionics technology. It offers a means of including the precision of the FMS-RNAV technology in the ATC system during the transition from today’s system to the future’s fully automated control system. This is an enabling technology that improves the ability to use and maintain FMS-RNAV in its role as a vital component of the ATC system. It has the potential to enhance future air traffic management-communication navigation surveillance concepts and applications.