On the performance evaluation of asynchronous processor architectures

Fine-Grained Parallel and Distributed Spatial Stochastic Simulation of Biological Reactions

Java bytecodes can be executed with the following three methods: a Java interpreter running on a particular machine interprets bytecodes; a Just-in-Time (JIT) compiler translates bytecodes to the native primitives of the particular machine and the machine executes the translated codes; and a Java processor executes bytecodes directly. The first two methods require no special hardware support for the execution of Java bytecodes and are widely used currently. The last method requires an embedded Java processor, picoJavaI or picoJavaII for instance. The picoJavaI and picoJavaII are simple pipelined processors with no ILP (instruction level parallelism) and TLP (thread level parallelism) supports. A so-called MAJC (microprocessor architecture for Java computing) design can exploit ILP and TLP by using a modified VLIW (very long instruction word) architecture and vertical multithreading technique, but it has its own instruction set and cannot execute Java bytecodes directly. In this paper, we investigate a processor architecture which can directly execute Java bytecodes meanwhile can exploit Java ILP and TLP simultaneously. The proposed processor consists of multiple slots implementing horizontal multithreading and multiple functional units shared by all threads executed in parallel. Our architectural simulation results show that the Java processor could achieve an average 20 IPC (instructions per cycle), or 7.33 EIPC (effective IPC), with 8 slots and a 4-instruction scheduling window for each slot. We also check other configurations and give the utilization of functional units as well as the performance improvement with various kinds of working loads.

In this paper, the scheduled dataflow (SDF) architecture-a decoupled memory/execution, multithreaded architecture using nonblocking threads-is presented in detail and evaluated against superscalar architecture. Recent focus in the field of new processor architectures is mainly on VLIW (e.g., IA-64), superscalar, and superspeculative designs. This trend allows for better performance, but at the expense of increased hardware complexity and, possibly, higher power expenditures resulting from dynamic instruction scheduling. Our research deviates from this trend by exploring a simpler, yet powerful execution paradigm that is based on dataflow and multithreading. A program is partitioned into nonblocking execution threads. In addition, all memory accesses are decoupled from the thread's execution. Data is preloaded into the thread's context (registers) and all results are poststored after the completion of the thread's execution. While multithreading and decoupling are possible with control-flow architectures, SDF makes it easier to coordinate the memory accesses and execution of a thread, as well as eliminate unnecessary dependencies among instructions. We have compared the execution cycles required for programs on SDF with the execution cycles required by programs on SimpleScalar (a superscalar simulator) by considering the essential aspects of these architectures in order to have a fair comparison. The results show that SDF architecture can outperform the superscalar. SDF performance scales better with the number of functional units and allows for a good exploitation of Thread Level Parallelism (TLP) and available chip area.

Processor architectures that are capable to reconfigure their instruction set and instruction format dynamically at run time offer a new flexibility exploiting instruction level parallelism vs. thread level parallelism. Based on the characteristics of an application or thread the instruction set architecture (ISA) can be adapted to increase performance or reduce resource/power consumption. To benefit from this run-time flexibility automatic selection of an appropriate ISA for each function of a given application is envisioned. This demands a cycle-accurate simulator that is capable of measuring the performance characteristics of an ISA dependent on the target application. However, simulation speed of a cycle-accurate simulator of our reconfigurable VLIW-like processor instances featuring dynamic operation execution would become relatively slow due to the superscalar-like microarchitecture. Within this paper we address this problem by presenting our cycle-approximate simulator approach containing a heuristic dynamic operation execution and memory model that provides a good trade-off between performance and accuracy. Additionally, the simulator features measurement of instruction level parallelism (ILP) that could be theoretically exploited by VLIW processor instances running on our architecture. The theoretical ILP could be used as an indicator for the ISA selection process without the need to simulate any combination of the different ISAs and applications.

Superscalar out-of-order cores deliver high performance at the cost of increased complexity and power budget. In-order cores, in contrast, are less complex and have a smaller power budget, but offer low performance. A processor architecture should ideally provide high performance in a power- and cost-efficient manner. Recently proposed slice-out-of-order (sOoO) cores identify backward slices of memory operations which they execute out-of-order with respect to the rest of the dynamic instruction stream for increased instruction-level and memory-hierarchy parallelism. Unfortunately, constructing backward slices is imprecise and hardware-inefficient, leaving performance on the table.\n\nIn this paper, we propose Forward Slice Core (FSC), a novel core microarchitecture that builds on a stall-on-use in-order core and extracts more instruction-level and memory-hierarchy parallelism than slice-out-of-order cores. FSC does so by identifying and steering forward slices (rather than backward slices) to dedicated in-order FIFO queues. Moreover, FSC puts load-consumers that depend on L1 D-cache misses on the side to enable younger independent load-consumers to execute faster. Finally, FSC eliminates the need for dynamic memory disambiguation by replicating store-address instructions across queues. FSC improves performance by 9.7% on average compared to Freeway, the state-of-the-art sOoO core, across the SPEC CPU2017 benchmarks, while incurring reduced hardware complexity and a similar power budget.

Compared to its synchronous counterpart, asynchronous design potentially provides many advantages in terms of power consumption, execution speed, and circuit reliability. This paper presents and discusses a complete new asynchronous circuit design flow of an 8-point Fast Fourier Transform circuit, a common building block in digital signal processing applications, starting from the radix-2 8-point decimation-in-time Fast Fourier Transform algorithm development to the final asynchronous gate netlist implementation and verification. The asynchronous hardware implementation is based on Null Convention Logic design methodology, a Quasi-Delay-Insensitive asynchronous design paradigm that has accomplished important advancements in recent years. The coarse-grained Null Convention Logic based 8-point Fast Fourier Transform circuit, implemented in a built-in commercial 65 nanometers process cell library, is functionally correct compared to its synchronous equivalent and can work at the maximum frequency of 8 Megahertz.

Exploitation of instruction-level parallelism is an effective mechanism for improving the performance of modern super-scalar/VLIW processors. Various software techniques can be applied to increase instruction-level parallelism. This paper describes and evaluates a software technique, dynamic memory disambiguation, that permits loops containing loads and stores to be scheduled more aggressively, thereby exposing more instruction-level parallelism. The results of our evaluation show that when dynamic memory disambiguation is applied in conjunction with loop unrolling, register renaming, and static memory disambiguation, the ILP of memory-intensive benchmarks can be increased by as much as 300 percent over loops where dynamic memory disambiguation is not performed. Our measurements also indicate that for the programs that benefit the most from these optimizations, the register usage does not exceed the number of registers on mast high-performance processors.

Division operation is very important in the computer system. Nowadays people use a hardware module─divider to implement the division algorithm. Conventionally synchronous techniques are applied to implement the divider. The synchronous systems always need system clock signals to trigger the system. However, the system clock of the synchronous system may cause some problems, such as clock skew, dynamic power consumption, ..., etc. Compared to synchronous systems, asynchronous circuits do not need system clock signals and thus the asynchronous system does not have the shortcomings mentioned above. Here we will propose a new asynchronous architecture for the divider. In this asynchronous scheme, the architecture is of simplicity and is very easy for the VLSI implementation. By this asynchronous architecture, we use TSMC’s 0.6um SPDM process to design a 32-b/32-b radix-2 non-restoring divider and the spice simulation proves it works. The HSPICE simulation shows that it can finish a 32-b/32-b division in between 3.7ns to 160.2ns.

Current mobile phone applications demand high performance from the DSP, and future generations are likely to require even greater throughput. However, it is important to balance these processing demands against the requirement of low power consumption for extended battery lifetime. A novel low‐power digital signal processor (DSP) architecture CADRE (Configurable Asynchronous DSP for Reduced Energy) addresses these requirements through a multi‐level power reduction strategy. A parallel architecture and configurable compressed instruction set meets the throughput requirements without excessive program memory bandwidth, while a large register file reduces the cost of data accesses. Sign‐magnitude representation is used for data, to reduce switching activity within the datapath. Asynchronous design gives fine‐grained activity control without the complexities of clock gating, and gives low electromagnetic interference. Finally, the operational model of the target application allows for a reduced interrupt structure, simplifying processor design by avoiding the need for exact exceptions.

In this paper, we propose a new asynchronous method based on a Null Convention Logic (NCL) to improve power consumption for low power integrated circuits. The reason is because the NCL based designs do not use a clock, it eliminates the problems related to the clock and its power consumption reduces significantly. To show the advantages of the selected method, we propose two design models using the synchronous circuit design method, and the NCL based asynchronous circuit design method. To test these two design models conveniently, we also propose an extra automatic test model. In this study, the AES decryption is used as an example to illustrate both methods. The two above proposed AES decryption models are simulated and synthesized at the various corners by VCS and Design Compiler tool using TSMC standard cell libraries in 65nm technology. The synthesis results of the two above mentioned models indicated that the power consumption of the NCL based asynchronous circuit model is 3 times lower than that of the synchronous circuit model, and significantly improves (from 94% to 98%) compared with the results of the other authors. The processing speed of the NCL based asynchronous circuit paradigm is able to achieve a maximum speed.

This work proposes automatic test pattern generation (ATPG) for Null Convention Logic (NCL). NCL is a robust asynchronous paradigm that introduces new challenges to test and testability algorithms due to the lack of a clock signal and the presence of a large number of state holding elements. The main features of this work are clockless, self-timed ATPG for all single stuck-at faults in NCL circuits, including those of gate internal feedback (GIF). The detection of faults on GIF is performed with no added test hardware. To the extent of our knowledge, this is the first work which has addressed clockless, self-timed ATPG with coverage for faults on GIF of NCL gates and with no area overhead. The proposed test generation algorithms are evaluated for several real-size NCL circuits with average 96.2% fault coverage.

A number of compute-intensive applications suffer from performance loss due to the lack of instruction-level parallelism in sequences of dependent instructions. This is particularly accurate on wide-issue architectures with large register banks, when the memory hierarchy (locality and bandwidth) is not the dominant bottleneck. We consider two real applications from computational biology and from cryptanalysis, characterized by long sequences of dependent instructions, irregular control-flow and intricate scalar and array dependence patterns. Although these applications exhibit excellent memory locality and branch-prediction behavior, state-of-the-art loop transformations and back-end optimizations are unable to exploit much instruction-level parallelism. We show that good speedups can be achieved through deep jam, a new transformation of the program control- and data-flow. Deep jam combines scalar and array renaming with a generalized form of recursive unroll-and-jam; it brings together independent instructions across irregular control structures, removing memory-based dependences. This optimization contributes to the extraction of fine-grain parallelism in irregular applications. We propose a feedback-directed deep jam algorithm, selecting a jamming strategy, function of the architecture and application characteristics.

The cellular iterative computation model bears upon three broad-ranging application domains: pixel-level image processing, finite-difference approximation of continuum problems (boundary value PDEs) in computational physics, and cellular automata as discrete models of complex locally-interacting systems, aimed at probing their emergent collective properties. The common underlying idea is to compute the global dynamics of a lattice-structured state-space through the iterative propagation of purely local computational dependencies between state-components. A past generation of mesh-connected SIMD array-processors, among which the MPP [Bat 80], CLIP [Pre 84] and CAM [Tof 87] machines, were canonical architectural mappings of this fruitful concept. All were fine-grain synchronous solutions. The new generation of MIMD RISC-based parallel computers that superseded them are essentially coarse-grain and asynchronous; They can simulate a cellular iterative model in a parallel pseudo-synchronous SPMD mode with global coordination mechanisms. A fine-grain asynchronous architectural model departs in a somewhat paradoxical way from these two mainstream approaches. The idea is to match an architecture with a functional concept of a synchronism, specific to cellular relaxation algorithms. As we show in the following, benefits accrue at both levels from this matching.

In contrast to traditional Parallel Discrete Event Simulation (PDES) systems using dedicated machines, an alternative master/worker approach for high throughput execution on shared computing platforms is proposed. Master/worker systems offer potential advantages over traditional PDES systems such as better support for heterogeneous machines, client-driven load balancing, fault tolerance, and execution on non-dedicated machines. We examine feasibility of executing PDES codes on master/worker systems. We characterise application properties that are important for efficient execution and define suitable performance metrics. The Aurora Parallel and Distributed Simulation System utilising the master/worker approach is described along with performance measurements in executing conservative PDES codes.

In parallel discrete event simulation techniques, the simulation model is partitioned into objects, concurrently executing events on different CPUs and/or multiple CPU-Cores. In. such a context, run-time supports for logical time synchronization across the different simulation objects play a central role in determining the effectiveness of the specific parallel simulation environment. hi this paper vile present an experimental evaluation of the memory management capabilities offered by the ROme OpTimistic Simulator (ROOT-Sim). This is an open source parallel simulation environment transparently supporting optimistic synchronization via recoverability (based on incremental log/restore techniques) of any type of memory operation affecting the state of simulation objects, i.e., memory allocation, deal-location and update operations. The experimental study is based on a synthetic benchmark which mimics different read/write patterns inside the dynamic memory map associated with the state of simulation objects. This allows sensibility analysis of time and space effects due to the memory management subsystem while varying the type and the locality of the accesses associated with event processing.