The Forward Slice Core Microarchitecture

Traditional program slicing techniques are crucial for early bug detection and manual/automated debugging of online code snippets. Nevertheless, their inability to handle incomplete code hinders their real-world applicability in such scenarios. To overcome these challenges, we present NS-Slicer, a novel learning-based approach that predicts static program slices for both complete and partial code Our tool leverages a pre-trained language model to exploit its understanding of fine-grained variable-statement dependencies within source code. With this knowledge, given a variable at a specific location and a statement in a code snippet, NS-Slicer determines whether the statement belongs to the backward slice or forward slice, respectively. We conducted a series of experiments to evaluate NS-Slicer's performance. On complete code, it predicts the backward and forward slices with an F1-score of 97.41% and 95.82%, respectively, while achieving an overall F1-score of 96.77%. Notably, in 85.20% of the cases, the static program slices predicted by NS-Slicer exactly match entire slices from the oracle. For partial programs, it achieved an F1-score of 96.77%–97.49% for backward slicing, 92.14%–95.40% for forward slicing, and an overall F1-score of 94.66%–96.62%. Furthermore, we demonstrate NS-Slicer's utility in vulnerability detection (VD), integrating its predicted slices into an automated VD tool. In this setup, the tool detected vulnerabilities in Java code with a high F1-score of 73.38%. We also include the analyses studying NS-Slicer’s promising performance and limitations, providing insights into its understanding of intrinsic code properties such as variable aliasing, leading to better slicing.

This paper uses a projection theory of slicing to formalize the definition of executable dynamic and forward program slicing. Previous definitions, when given, have been operational, and previous descriptions have been algorithmic. The projection framework is used to provide a declarative formulation in terms of the different equivalences preserved by the different forms of slicing. The analysis of dynamic slicing reveals that the slicing criterion introduced by Korel and Laski contains three inter-woven criteria. It is shown how these three conceptually distinct criteria can be disentangled to reveal two new criteria. The analysis of dynamic slicing also reveals that the subsumes relationship between static and dynamic slicing is more intricate that previous authors have claimed. Finally, the paper uses the projection theory to investigate theoretical properties of forward slicing. This is achieved by first re-formulating forward slicing to provide an executable forward slice. This definition allows for formal investigation of the relationship between forward and backward slicing

Exploitation of instruction-level parallelism is an effective mechanism for improving the performance of modern super-scalar/VLIW processors. Various software techniques can be applied to increase instruction-level parallelism. This paper describes and evaluates a software technique, dynamic memory disambiguation, that permits loops containing loads and stores to be scheduled more aggressively, thereby exposing more instruction-level parallelism. The results of our evaluation show that when dynamic memory disambiguation is applied in conjunction with loop unrolling, register renaming, and static memory disambiguation, the ILP of memory-intensive benchmarks can be increased by as much as 300 percent over loops where dynamic memory disambiguation is not performed. Our measurements also indicate that for the programs that benefit the most from these optimizations, the register usage does not exceed the number of registers on mast high-performance processors.

Java bytecodes can be executed with the following three methods: a Java interpreter running on a particular machine interprets bytecodes; a Just-in-Time (JIT) compiler translates bytecodes to the native primitives of the particular machine and the machine executes the translated codes; and a Java processor executes bytecodes directly. The first two methods require no special hardware support for the execution of Java bytecodes and are widely used currently. The last method requires an embedded Java processor, picoJavaI or picoJavaII for instance. The picoJavaI and picoJavaII are simple pipelined processors with no ILP (instruction level parallelism) and TLP (thread level parallelism) supports. A so-called MAJC (microprocessor architecture for Java computing) design can exploit ILP and TLP by using a modified VLIW (very long instruction word) architecture and vertical multithreading technique, but it has its own instruction set and cannot execute Java bytecodes directly. In this paper, we investigate a processor architecture which can directly execute Java bytecodes meanwhile can exploit Java ILP and TLP simultaneously. The proposed processor consists of multiple slots implementing horizontal multithreading and multiple functional units shared by all threads executed in parallel. Our architectural simulation results show that the Java processor could achieve an average 20 IPC (instructions per cycle), or 7.33 EIPC (effective IPC), with 8 slots and a 4-instruction scheduling window for each slot. We also check other configurations and give the utilization of functional units as well as the performance improvement with various kinds of working loads.

This paper evaluates and analyses the influence of an asynchronous control paradigm on the performance of processor architectures. The idea of a micronet is introduced which models the datapath as a network of concurrent functional units which communicate with each other asynchronously. This allows the efficient exploitation of fine-grained instruction-level parallelism (ILP). A macronet-based asynchronous processor (MAP) architecture is described in Occam2 and simulated in a parallel discrete event simulation environment. Suitable metrics are introduced for measuring the performance of the MAP datapath.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The dramatic increase in the number of heterogeneous computing architectures (HCAs) which include CPUs, GPUs, TPUs, FPGAs, and new neuromorphic processors has transformed the high-performance computing (HPC) and artificial intelligence (AI) workloads. As the complexity of architecture increases there is corresponding uncertainty on reliability and performance checks, particularly when systems are incorporated with different processing elements, interconnections, and memory levels. Modern non-deterministic or non-stochastic heterogeneous environments are associated with traditional reliability models that feel great necessity to model nonlinear interdependencies between components. The current paper proposes an innovative AI-based modeling framework that would be capable of measuring system reliability and performance indicators in the context of HCAs. The suggested solution merges Deep Neural Networks (DNNs), Bayesian Inference Models, and the strategies of Reinforcement Learning (RL) to forecast the increase of the system reliability, the performance bottlenecks, and the mean time between failures (MTBF) at the system level. To train AI models that can capture the multi-domain interactions of computation, communication, and thermal dynamics, a large-scale simulation dataset was created with synthetic benchmarks, actual workloads (SPEC ACCEL, MLPerf, HPCG), unlikely fault profiles, and injected fault profiles to have AI models that are trained to simulate interactions in large-scale systems. The approach puts the feature engineering of runtime telemetry (e.g., power, temperature, utilization) and hardware counters (e.g., instruction-level parallelism, cache miss rates) to construct predictive and adaptive reliability estimators. As opposed to the traditional models, our AI-based system advances its state dynamically with online learning methods of training, allowing its internal state to identify fault and self-optimize it. Findings suggest that the suggested AI system can make accurate predictions in both system performance degradation and reliability estimates with a success level of 96.8 and 94.2 per cent respectively when operating in a heterogeneous environment. Comparative research with classical models of reliability, i.e. Markov and Weibull-based models reveal high gains on adaptability, precision and generalization. Moreover, the optimization using reinforcement learning provided a 1525 percentage ratio in task scheduling performance expressed in a limited thermal and power budget. This article adds to the increasing overlap between system modeling based on AI and the optimization of heterogeneous computing, sets the stage of the introduction of new intelligent reliability management of data centers, autonomous computing systems, and HPC infrastructure

Processor architectures that are capable to reconfigure their instruction set and instruction format dynamically at run time offer a new flexibility exploiting instruction level parallelism vs. thread level parallelism. Based on the characteristics of an application or thread the instruction set architecture (ISA) can be adapted to increase performance or reduce resource/power consumption. To benefit from this run-time flexibility automatic selection of an appropriate ISA for each function of a given application is envisioned. This demands a cycle-accurate simulator that is capable of measuring the performance characteristics of an ISA dependent on the target application. However, simulation speed of a cycle-accurate simulator of our reconfigurable VLIW-like processor instances featuring dynamic operation execution would become relatively slow due to the superscalar-like microarchitecture. Within this paper we address this problem by presenting our cycle-approximate simulator approach containing a heuristic dynamic operation execution and memory model that provides a good trade-off between performance and accuracy. Additionally, the simulator features measurement of instruction level parallelism (ILP) that could be theoretically exploited by VLIW processor instances running on our architecture. The theoretical ILP could be used as an indicator for the ISA selection process without the need to simulate any combination of the different ISAs and applications.

Transistor budgets have been increasing at a very fast pace in the last years. This increasing transistor density will lead next generation processors to have a billion transistors available. It is the task of the computer architect to find the best way to use them.Out of order superscalar processors exploit parallelism at the finer grain, exploiting Instruction Level Parallelism (ILP). They issue multiple instructions per cycle, often in an order other than the specified by the programmer, using branch prediction and other speculative execution techniques in order to increase the available parallelism.Very Long Instruction Word (VLIW) processors also exploit parallelism at the instruction level, but they mostly rely on the compiler to detect the available parallelism. This increased compiler role allows a simpler design, and can be run at a faster clock rate, compensating for the loss of ILP.Chip Multiprocessors (CMP) join several narrow superscalar/VLIW components into a single processor, and mostly rely on the Thread Level Parallelism (TLP) for performance. The small and simple components can also run at a faster clock rate compensating for the loss of ILP, and significantly increasing throughput.Simultaneous Multithreaded (SMT) processors are based on wide superscalars, and exploit both ILP and TLP by issuing instructions from several different threads to the same pipeline, obtaining the benefits of TLP without sacrificing the ILP on single-threaded applications.For each of these options we will need to find the best balance between performance, design complexity, and power consumption among other factors. Also, the frontiers between them are not clear, and many intermediate design points can be found which leads to better/simpler/cheaper processors for the next generation of high performance computers.

Power is the most critical resource for the exascale high performance computing. In the future, system administrators might have to pay attention to the power consumption of the machine under different work loads. Hence, each application may have to run with an allocated power budget. Thus, achieving the best performance on future machines requires optimal performance subject to a power constraint. This additional performance requirement should not be the responsibility of HPC~(High Performance Computing) application developers. Optimizing the performance for a given power budget should be the responsibility of high-performance system software stack. Modern machines allow power capping of CPU and memory to implement power budgeting strategy. Finding the best runtime environment for a node at a given power level is important to get the best performance. This paper presents ARCS (Adaptive Runtime Configuration Selection) frameworkthat automatically selects the best runtime configuration for each OpenMPparallel region at a given power level. The framework uses OMPT (OpenMP Tools) API, APEX(Autonomic Performance Environment for eXascale), and Active Harmony frameworksto explore configuration search space and selects the best number of threads, scheduling policy, and chunk size for a given power level at run-time. We test ARCS using theNAS Parallel Benchmark, and proxy application LULESH with Intel Sandybridge, and IBM Power multi-core architectures. We show that for a given power level, efficient OpenMP runtime parameter selection can improve the execution time andenergy consumption of an application up to 40% and 42% respectively.

Growing demand for high performance in embedded systems is creating new opportunities for Instruction-Level Parallelism (ILP) techniques that are traditionally used in high performance systems. Predicated execution, an important ILP technique, can be used to improve branch handling, reduce frequently mispredicted branches, and expose multiple execution paths to hardware resources. However, there is a major tradeoff in the design of the instruction set, the addition of a predicate operand for all instructions. We propose a new architecture framework for introducing predicated execution to embedded designs. Experimental results show a 10% performance improvement and a code reduction of 25% over a traditionally predicated architecture.

It is important for computer architects to have a good understanding about the applications running on the designed hardware. That is to optimize their designs and run the applications more efficiently. Designing processors for accelerating big-data and cloud applications is a hot research topic. Currently, there are only a few papers on the analysis/characterizations of emerging big-data and cloud applications. Although these studies reveal the inefficiencies in a processor micro-architecture running big-data applications, they have been conducted using real-hardware, limiting the scope and flexibility of the analysis. In this paper, we aim to characterize a big-data workload using a novel method to simulate a distributed system and optimize an out of order core for running the cloud applications. dist-gem5, is a parallel and distributed version of gem5 which allows us to efficiently simulate a large scale distributed system on a cluster. Using dist-gem5, we aim to identify the bottlenecks and inefficiencies in the server processors and their overall system architecture, cutting across off-chip network stack, operating systems, Ethernet devices and core microarchitecture. Frist, we compare the results of a set of cloud application against SPECint2006 results. Our results show that BigData workloads, compared to SPECInt, has ∼3x and ∼4x more instruction cache miss rate and branch miss prediction rate, respectively. Next, we pick Memcached, as a representative BigData workload, and analyze how its performance and power scales with more cores under different request rates and core microarchitectures. Interestingly, we find out that having more cores on a chip does not bring more performance even for a parallel application like Memcached. A quad core ARM-v7 chip can have up to 6.5x longer average request latency compared to a single core ARM-v7 chip. We find that L2 cache architecture is the bottleneck in the ARM-v7 multi-core system and fixing that can make the performance of an embedded core as good as a high performance O3 core running Memcached server.

A high performance ECC hardware implementation with instruction-level parallelism over GF(2 163)

As the technology is advancing day by day, the need of high performance devices is also increasing. High performance is achieved at the expense of high power dissipation. Nowadays, field programmable gate arrays (FPGAs) are widely used in wireless communication systems due to their low non-recurring cost and high operating speed. There are many high performance applications (i.e., image processing, digital signal processing, wireless transceivers etc.) in which FPGAs are widely used. However, their complex architectures lead to high power consumption. Estimation of power in the early stage of the design flow would help designers to design the systems as per specified power budget. Therefore, two different approaches for power estimation are proposed in this paper. First is the heuristic approach based on back propagation neural network and second is the regression based statistical approach. It is observed that heuristic approach is better as compared regression in terms of power estimation of most of the digital circuits considered in this work.

High-performance single-threaded processors achieve their performance goal partly by relying, among other architectural techniques, on speculation and large on-chip caches. The hardware to support these techniques is usually a large portion of the overall processor real state area, and therefore it consumes a significant amount of power that sometimes is not optimally used toward doing useful work. In this work, we study the intuitive fact that architectures with hardware support for threads are more power efficient than a more traditional single-threaded superscalar architecture. Toward this goal, we have created a model of the power, performance and area of several parallel architectures. This model shows that a parallel architecture can be designed so that (a) it requires less area and power (to reach the same performance), or (b) it achieves better power efficiency and less area (for the same power budget), or (c) it has higher performance and better power efficiency (for the same area constraint), when compared to a single-threaded superscalar architecture.

A large portion of the power consumption of data centers can be attributed to cooling. In dynamic thermal management mechanisms for data centers and servers, thermal setpoints are typically chosen statically and conservatively, which leaves significant room for improvement in the form of improved energy efficiency. In this paper, we propose two hierarchical thermal-aware power optimization techniques that are complementary to each other and achieve (i) lower overall system power with no performance penalty or (ii) higher performance within the same power budget. At the data center level, we trade off facility Heating, Ventilation and Air Conditioning (HVAC) power with server fan power by choosing between two thermal setpoints for the HVAC chiller based on the cooling zone utilization levels. This optimization can reduce total data center total power by as much as 12.4%-17%, with no performance penalty. At the server level, we trade off fan power and circuit leakage power by dynamically adjusting the server thermal setpoint, allowing the system to heat up when this saves more fan power than it costs in terms of leakage power. We evaluate this optimization on an IBM POWER 750 and find that it reduces total server power by up to 5.4% with no performance penalty for workloads that heavily exercise a server.