Optimization of Asynchronous FIFO Design Difficulties Using Verilog HDL

With the high-speed development of integrated circuits, digital systems are growing in size and complexity. In complex digital systems, different modules may run under different clock domains. For example, in a communication system, the data receiving module and the data processing module may be driven by different clocks, where it requires an effective data caching mechanism to coordinate data transfer between different clock domains. Asynchronous FIFO meets this need. It can securely store and transfer data between different clock domains, reducing the possibility of data loss and errors. This paper gives a comprehensive review of the design of asynchronous FIFO, and summarizes the characteristics and advantages of asynchronous FIFO in a metastable state, empty-full signal creation, low latency, high throughput, parameterizable design, and the performance of different design methods and application scenarios by analyzing several related research results. The purpose is to provide a reference for further research and application of asynchronous FIFO.

Universal Asynchronous Receiver Transmitter (UART) is widely used in data communication process especially for its advantages of high reliability, long distance and low cost. In this paper, we present the design of 9-bit UART modules based on Verilog HDL. This design features automatic address identification in the character itself. We have implemented the VLSI design of the module and pass data between the proposed 9-bit UART module with a host CPU. The design consists of receiver module, transmitter module, prescaler module and asynchronous FIFOs. We have explained the functions of each individual sub-modules and how the design works in simulation.

The quality of shortwave channels may vary considerably due to the time-specific changes of the transmission conditions. So the correct transmission of a continuous data stream, e.g. digitized speech signals output by a vocoder cannot be guaranteed under adverse conditions even by means of complex error correction measures or costly high transmitter power. This results in the loss of vocoder data-the transmission of speech information is partly or fully interrupted which impairs intelligibility. For this reason we propose a voice transmission system as a solution to the problem of correct voice data transmission. It is a method that offers quasi-real-time behaviour for channels that are subject to no interference or only slight interference, and that offers complete and correct data transmission with reduced real-time behaviour (mailbox operation) in the presence of strong or long-term interference and fading. To reach intelligibility at the transmitter end, the vocoder data are first divided into intelligible blocks, e.g. into coherent words between two speech pauses and stored in a buffer. The blocks are then transferred to the lower layers of the ISO/OSI reference model where an ARQ protocol is employed which leads to correct data transmission. At the receiver end, the blocks can then be listened to individually or as a whole and, if necessary, repeated once or several times (mailbox operation). This method was tested over a radio link of 800 km between Rostock University and Rohde & Schwarz Munich laboratory. 1200 bps vocoders from Comsat Co. and XK 2100 transceivers with packet radio protocol (PRP) RSX.25 from Rohde & Schwarz were used.

2 - Input—output devices

Recent development in artificial neural networks has led to an increase in performance, but also in complexity and size. This poses a significant challenge for the exploration and analysis of the spatial structure and temporal behaviour of such networks. Several projects for the 3D visualisation of neural networks exist, but they focus largely on the exploration of the spatial structure alone, and are using standard 2D screens as output and mouse and keyboard as input devices. In this article, we present NeuVis, a framework for an intuitive and immersive 3D visualisation of spiking neural networks in virtual reality, allowing for a larger variety of input and output devices. We apply NeuVis to NeuCube, a 3-dimensional spiking neural network learning framework, significantly improving the user’s abilities to explore, analyse, and also debug the network. Finally, we discuss further venues of development and alternative render methods that are currently under development and will increase the visual accuracy and realism of the visualisation, as well as further extending its analysis and exploration capabilities.

We present a tangible user interface based upon mediaBlocks: small, electronically tagged wooden blocks that serve as physical icons (“phicons”) for the containment, transport, and manipulation of online media. MediaBlocks interface with media input and output devices such as video cameras and projectors, allowing digital media to be rapidly “copied” from a media source and “pasted” into a media display. MediaBlocks are also compatible with traditional GUIs, providing seamless gateways between tangible and graphical interfaces. Finally, mediaBlocks act as physical “controls” in tangible interfaces for tasks such as s equencing collections of media elements. CR Categories and Subject Descriptors: H.5.2 [User Interfaces] Input devices and strategies; H.5.1 [Multimedia Information Systems] Artificial, augmented, and virtual realities Additional Keywords: tangible user interface, tangible bits, phicons, physical constraints, ubiquitous compu ting

This paper presents the design and implementation of a 128-bit Asynchronous Gray Code FIFO using Verilog HDL. The FIFO is designed for bidirectional transfer of data between different clock domains using dual-port RAM memory and gray code for specifying empty and full conditions. To avoid metastability, two 2D flip-flops are used as synchronizers. The design is optimized for speed and efficiency using universal gates and status flags Also, the simulation provides the threshold status flags for write and read operations is 10% and 90%, respectively. The simulation and verification of the design are performed using Xilinx Vivado software and virtually implemented for the Artix 7 Low Voltage FPGA. The design is scalable for larger memory requirements.

This paper proposes the design of robust and highly reliable oil leakage detection with optimal performance in faulty and normal conditions. Flow rates and sound are two parameters considered for the design of this project. The purpose of this design is to ensure that faults do not result in malfunctioning and system failure and to achieve the best performance even with minimum number of input and output devices working properly. The fault detection and isolation (FDI) problem is an inherently complex one and for this reason, the immediate aims are to preserve the stability of the process and if it is possible, to control and continue the process in a slightly degraded manner. The role of the FDI algorithms is to ensure that the control equipment must make correct decision. This system has two flow stations that are connected by a pipeline and flow rate difference is used to detect leakage. First flow station has 2 sound alarms and pumps as output devices and 2 flow meters and start button as input devices. Also the second flow station has the same arrangement as the first flow station except that it does not have a pump. Both flow stations use mobile phones as modems to send and receive short message services. The essence of the two flow meters and two sound alarms at each of the flow stations is to ensure optimal performance and robustness even if one or more of the devices failed. Once, the system starts, the first flow station pumps crude oil to the second flow station while the former also sends the flow rate at its end M1 to the later. Then, the second flow station measures its flow rate as M2 and compares it with M1 so as to check whether the difference is still within the allowable threshold. If the difference between M1 and M2 is within the allowable threshold, the system continues working but once the difference is above the recommended threshold, the second flow station sends short message services (sms) to the first flow station and equally alerts its workers using sound alarm. Then the first flow station switches off the pump and equally alerts its worker that leakage has occurred using the sound alarms. The developed system showed that at sensors (input devices) and actuators (output devices) reliabilities of 50% and above, the system efficiency was up to 95%. This system would go a long way to ensure robust oil leakage detection in our oil industries, if implemented.

In video encoding hardware system based on camera link interface, in order to coordinate data transmission between different clock domains, we designed a DSP and FPGA interconnection scheme, in which a software FIFO was used. This article introduced relevant interface interconnects and timing analysis. The system we are using proved the method introduced in the article is stable and efficient to guarantee the speed and correctness of data transmission.

The availability of consumer-level devices for both visualising and interacting with Virtual Reality (VR) environments opens the opportunity to introduce more immersive contents and experiences, even on the web. For reaching a wider audience, developing VR applications in a web environment requires a flexible adaptation to the different input and output devices that are currently available. This paper examines the required support and explores how to develop VR applications based on web technologies that can adapt to different VR devices. We summarize the main engineering challenges and we describe a flexible framework for integrating and exploiting various VR devices for both input and output. Using such framework, we describe how we re-implemented four manipulation techniques from the literature to enable them within the same application, providing details on how we adapted its parts for different input and output devices such as Kinect and Leap Motion. Finally, we briefly examine the usability of the final application using our framework.

The color transformation module is important in Color Hard Copy system. The objective of the module is to get the minimum of the color difference between the color signals represented in input devices and output devices. In the proposed method, the color transformation module is implemented in order to reduce the developing time and has the flexibility to modify the module's components. The module performs gamma correction and color matching algorithm whose data is fed and outputted with look-up tables. The table-based color matching approach is to decrease complexity and cost in hardware implementation. In fact, Most of color devices are given linear input signals, but the output color signals are not linear corresponding to the input, even they are centered on some regions within the gamut of the output device. The relationship between the input and output color signals is approximately a gamma curve in the proposed experiments, so the problem can be resolved roughly by the one-dimension gamma correction. The three-dimension color matching algorithm is performed in the uniform color spaces (CIE Lab, CIE Luv) whose color difference is more closely correlated with the perceptual difference. In general, color calibration must be run in such color spaces that the color difference can be quantized to referable values corresponding to the perceptual difference. The Gray Component Replacement theory will be used in processing color separation. The proposed color transformation module can efficiently improve color calibration from the average color difference about 58 down to about 4 for color output devices in the proposed experiments.

Introduction: business computing essentials. Hardware - input devices, processors, output devices, memory and storage media communications / software - operating systems, programming languages, application packages general tools specific tools specific applications the management of business computing.

This work presents novel achievable schemes for the 2-user symmetric linear deterministic interference channel with limited-rate transmitter cooperation and perfect secrecy constraints at the receivers. The proposed achievable scheme consists of a combination of interference cancelation, relaying of the other user's data bits, time sharing, and transmission of random bits, depending on the rate of the cooperative link and the relative strengths of the signal and the interference. The results show, for example, that the proposed scheme achieves the same rate as the capacity without the secrecy constraints, in the initial part of the weak interference regime. Also, sharing random bits through the cooperative link can achieve a higher secrecy rate compared to sharing data bits, in the very high interference regime. The results highlight the importance of limited transmitter cooperation in facilitating secure communications over 2-user interference channels.

Chapter 14 explained how data in parallel form may be transmitted from and received by a microcomputer. All the lines of a port are simultaneously sending or receiving data. In contrast, the serial mode of data transmission sends bits of data one at a time along a single conductor, as in Fig. 15-1a. A high voltage may appear at one time and a low voltage an instant later, as shown in Fig. 15-1b. If the voltage is high for 1/300 s, in one type of serial data transmission, for example, that signal could mean a 1 and if low it could mean a zero. A high voltage for 1/150 s is interpreted as two 1’s in succession. Instead of a voltage signal, pulses of current and the lack of them could indicate 0’s and 1’s. Sending parallel data requires eight conductor lines, while a rudimentary system transmitting serial data requires only one line plus a ground line.

In a recent era of modern technology, there are many problems for storage, retrieval and transmission of data. Data compression is necessary due to rapid growth of digital media and the subsequent need for reduce storage size and transmit the data in an effective and efficient manner over the networks. It reduces the transmission traffic on internet also. Data compression try to reduce the number of bits required to store digitally. The various data and image compression algorithms are widely use to reduce the original data bits into lesser number of bits. Lossless data and image compression is a special class of data compression. This algorithm involves in reducing numbers of bits by identifying and eliminating statistical data redundancy in input data. It is very simple and effective method. It provides good lossless compression of input data. This is useful on data that contains many consecutive runs of the same values. This paper presents the implementation of Run Length Encoding for data compression.