Research Progress of Asynchronous FIFO Design

FIFO is a first-in first-out data storage and buffer, which can cache the continuous data stream to prevent data loss during incoming and storing operations. A special interface technology, asynchronous FIFO, needs to be introduced to ensure the correct data transmission when data needs to be transmitted between different clock domains or when the input device and the output device do not match the data interface width. This paper uses Verilog HDL language to design an asynchronous FIFO which can realize the conversion of different data bit widths. In the paper, the difficulties of this design are analyzed in detail, including the method of synchronizing different clock domains, the judgment of FIFO's empty and full state, the method of reducing metastability during data transmission and the method of data bit width conversion. Finally, the designed program is simulated and verified by modelsim software, and the waveform results obtained by simulation are analyzed in detail.

The article discusses ways to optimize the performance of information communication systems, which includes increasing spectral efficiency and reliability while minimizing delay and energy consumption due to the full integration of communication and scanning services. The functioning algorithm of the integrated scanning and communication system and the organization scheme of the communication mode using the scanning process based on the proposed generalized model of the integrated scanning and data transmission system are considered. Ways to improve the efficiency of telecommunication systems due to the joint use of communication and scanning tools with the best compromise between scanning characteristics and the bandwidth of the transmission channel are considered. Peculiarities of improving wireless communication systems with regard to high data transfer rates, low latency and wide connection possibilities are studied. In particular, access to other system functions, such as scanning/visualization and localization, is justified. Due to the considered innovative applications, the possibility of increasing the performance of the integrated wireless scanning and communication system (ISAC) is determined. The researched positioning process in 5G is proposed to be expanded due to additional detection functions, in particular with the use of new metrics such as accuracy and resolution. New KPIs in 6G networks are considered, replacing the KPI of positioning accuracy in 5G. As a result, key performance indicators based on different application scenarios are proposed, the accuracy of which should be from 1 to 10 cm, and the resolution should be up to 1 mm. The potential of the new ISAC technology was investigated, in particular, the features of the coexistence of communication and scanning modules in an integrated solution at the system level and methods of increasing the efficiency of coexistence at the system level were considered; justification of a positive result from an integrated system solution for communication and scanning services; advantages and disadvantages of existing communication and scanning systems with implemented integration at the system level. The obtained results of research on the integration of communication and scanning means, in particular: the analysis of the performance of generalized ISAC networks and the conclusions about the fundamental limits of performance obtained for a simple structure made it possible to determine the best compromise between the characteristics of scanning and the bandwidth of the communication channel, provided an opportunity to create practical schemes, which approximate a compromise of waveforms, coding tables, structures and protocols.

Modern digital systems become more complex with increasing multi-clocking techniques for better performance. Multiple asynchronous clock domains have been using for different I/O interface in today's modern system on chip (SoC). Each system needs to communicate with one or other system/peripherals continuously. These multiple asynchronous clock domains are facing meta-stability, data losses and other clock domain crossing (CDC) issues. CDC is an important issue in all today's SoC. To overcome the clock domain crossing(CDC) issues such as meta-stability and data losses, basic two flip-flop synchronizer has been designed whose performance is depends on pulse width of transmitting signal across the different clock domains, which has to be greater than 1.5X the receiver domain clock width. In this paper a short pulse synchronizer has been designed and demonstrated for variable pulse width, whose performance is independent on pulse width of the signal which transmits across the domains.

Living cells generate the cell cycle or apoptosis, depending on the course will be repeated. If an error occurs during this period of life in order to maintain the cells in the peripheral cells find the error portion. These cellular functions were applied to the system to simulate the circuit. Circuit implementation of the present study was constructed the redundant structure in order to found the error quickly. Self-repairing of digital systems as an advanced form of fault-tolerance has been increasingly receiving attention according as digital systems have been more and more complex and speed-up especially for urgent systems or those working on extreme environments such as deep sea and outer space. Simulating the process of cell differentiation algorithm was confirmed by the FPGA on the counter circuit. If an error occurs on the circuit where the error was quickly locate and repair. In this paper, we propose a novel self-repair architecture for fast and robust fault-recovery that can easily apply to real, complex digital systems. These Self-Repairing Algorithms make it possible for the application digital systems to be alive even though in very noisy and extreme environments.

The broadband aeronautical multi-carrier communications (B-AMC) system is a promising candidate for the future L-band radio system called L-band digital aeronautical communications system (L-DACS). In this paper, the design of the physical (PHY) as well as of the data link layer (DLL) is addressed. As B-AMC is intended to be operated in the L-band between two adjacent distance measuring equipment (DME) channels, the avoidance of mutual interference between existing L-band systems and B-AMC has been in the focus of the PHY layer design. In order to demonstrate the feasibility of the coexistence with DME, a draft frequency planning has been performed for Europe, resulting in successful frequency assignments in wide parts of Europe. The B-AMC DLL supports data link communication with low latency and high throughput. It is designed to be highly configurable and to support different service requirement sets and traffic profiles. In this paper, the current DLL configuration featuring a low RL duty-cycle and graceful degradation is discussed in detail.

: As the U.S. Army continues to develop more powerful and complex digital information systems, it is essential that both training needs and training opportunities are addressed to meet mission objectives. One way to address the training challenges of emerging digital systems is through the use of computer-based instruction (CBI), particularly because of the flexibility it offers in the way training can be delivered (e.g., embedded, distance learning, Internet). Another way is to improve learning by applying principles of cognitive psychology to the training design. This paper describes a research and development effort that incorporated a limited set of cognitive learning principles and techniques in the design of CBI for individual digital operator skills. To demonstrate the design features, four prototype training modules were developed for the Force XXI Battle Command Brigade and Below (FBCB2), the Army's vehicle-mounted digital system for distributing information to provide situational awareness. This paper describes how the selected instructional techniques and cognitive principles were used in distributed computer-based training. Pictures of screen layouts illustrate how the principles and techniques were instantiated in operator training for a digital system. Finally, this report provides a discussion of the lessons learned and issues for future research and development.

Multi-clock is commonly used in complex systems. So if synchronous signals in one clock domain are transferred to another clock domain, they will become asynchronous signals. Asynchronous signals will cause metastable state, which will lead to unpredictable results. How metastabilities led to errors in a system is described first. Then a simulation of RS flip flop using pspice is to show the detail procedure of metastability. To demonstrate how often metastabilities will happen, a FPGA based experimentation is realized by changing the internal layout of flip flop manually, which changes the propagation delay between them.

Performance analysis of ZigBee network topologies for underground space monitoring and communication systems

A high speed digital data acquisition system for the Indian National Gamma Array at Tata Institute of Fundamental Research

Software-Defined Internet of Vehicles (SD-IoV) is an emerging technology that is being used in modern intelligent transportation systems (ITS). The ultimate goal of SD-IoV is to provide seamless connectivity to the end-users with low latency and high-speed data transfer. However, due to the increase in the density of the connected IoV using an open channel, i.e., the Internet, the foremost challenges of high power consumption and secure data transfer are inevitable in such an environment. An external eavesdropper may intercept the transmitted message to access the legitimate information over the public channel, i.e., the Internet. Most of the solutions reported in the literature to tackle these issues may not be applicable in the SD-IoV environment due to high computation and communication costs. Motivated from this, in this paper, the problems of high power consumption and secure data transfer in SD-IoV are formulated using mixed-integer non-linear programming (MINLP) with associated constraints. To solve the aforementioned problem, we propose a joint power optimization and secrecy ensured scheme known as <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SecGreen</i> . <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SecGreen</i> has an efficient energy harvesting algorithm using simultaneous wireless information and power transfer (SWIPT) to maximize the energy efficiency. Moreover, to mitigate various security attacks, a resilient lightweight secrecy association protocol is designed between vehicle and trusted gateway node of SD-IoV so that only trusted vehicles can communicate with each other and with the nearest base stations. The secrecy association protocol uses security primitives such as– physically unclonable function (PUF), one-way hash function, and bitwise exclusive OR (XOR) operations which are suitable for energy-constraint sensors in SD-IoV. The performance of the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SecGreen</i> is compared with the existing schemes, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Stable &amp; Scalable Link Optimization (SSLO), and Secure &amp; Energy-Efficient Blockchain-enabled (SEEB)</i> respectively. The result shows that when the number of packets across the subchannel increases, the energy consumption increases. Also, the result shows that the proposed scheme attains 22.5% and 20.34% better energy efficiency as compared to SSLO and SEEB schemes, respectively. In addition, the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SecGreen</i> scheme achieves 37.48% and 32.15% higher throughput as compared to SSLO and SEEB schemes. The results obtained show the superior performance of the proposed <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SecGreen</i> scheme in comparison to these existing competitive schemes in the literature.

With the rapid development of multi-core processor technology, parallelization has become the main approach for modern applications to improve throughput and responsiveness. However, the increasing number of processors also poses a challenge to the scalability of parallel program performance. In a traditional single-threaded program, all data is exclusively occupied by one thread, so the performance optimization of the program mainly focuses on the algorithm logic and implementation skills of the program; while in the multi-core system environment, most multi-threaded applications have performance scalability bottleneck. That is, the application cannot make full use of the performance advantages of multiple cores, and its performance decreases as the number of processors increases. The key factor restricting the improvement of performance scalability is often the synchronization mechanism of multi-core systems. Reader-writer lock is a synchronization mechanism that divides the operation to access shared resources or data into reader lock and writer lock, which enables effective cooperation between multiple different threads and ensures that applications can operate in a multicore environment with logical consistency. However, from another perspective, the reader-writer lock mechanism also limits the scalability of concurrent execution of applications. In application scenarios with different reader/writer ratios, the performance of reader-writer locks also differs, restricting the scalability of the performance of applications in multicore systems. Therefore, in a multi-core environment, it is of practical significance to implement a new type of readerwriter lock with scalable performance. This new reader-writer lock may automatically adjust the lock acquisition path according to the read/write ratio of the application scenario. In view of the shortcomings of the current reader-writer locks, this paper proposes a simple, efficient, optimized, and easy-to-implement adaptive reader-writer lock mechanism and interface which is suitable for multi-core environments, as well as application scenarios with different read/, write ratios. This mechanism gives full play to the high performance of multi-core systems and automatically adjusts lock acquisition according to different application scenarios. There are only minor changes to the application by replacing the original reader-writer lock instance and API interface function calls with an adaptive reader-writer lock instance and the API interface function calls for the adaptive reader-writer lock. The mechanism enables good scalability and improves the concurrency and scalability of reader-writer locks in multi-core systems in application scenarios with different read/write ratios. It will be conducive to meeting the growing demand for low latency, high throughput, and high concurrency processors.

The 5G user plane function (UPF) is a critical inter-connection point between the data network and cellular network infrastructure. It governs the packet processing performance of the 5G core network. UPFs also need to be flexible to support several key control plane operations. Existing UPFs typically run on general-purpose CPUs, but have limited performance because of the overheads of host-based forwarding. We design Synergy, a novel 5G UPF running on SmartNICs that provides high throughput and low latency. It also supports monitoring functionality to gather critical data on user sessions for the prediction and optimization of handovers during user mobility. The SmartNIC UPF efficiently buffers data packets during handover and paging events by using a two-level flow-state access mechanism. This enables maintaining flow-state for a very large number of flows, thus providing very low latency for control and data planes and high throughput packet forwarding. Mobility prediction can reduce the handover delay by pre-populating state in the UPF and other core NFs. Synergy performs handover predictions based on an existing recurrent neural network model. Synergy's mobility predictor helps us achieve 2.32× lower average handover latency. Buffering in the SmartNIC, rather than the host, during paging and handover events reduces packet loss rate by at least 2.04×. Compared to previous approaches to building programmable switch-based UPFs, Synergy speeds up control plane operations such as handovers because of the low P4-programming latency leveraging tight coupling between SmartNIC and host.

Achieving higher levels of plasma performance control in present fusion experiments requires that diagnostics be upgraded to deliver processed physical parameters in real-time (RT). A key element in a diagnostic RT upgrade is the data acquisition system (DAS), that should be capable of delivering the acquired data to the data processing resources with very low latencies and in the shortest possible time. Adequate standard commercial solutions with these characteristics are not easily found in the market, what leads most of the times to the development of complex custom high-performance designs from ground-up. A mixed solution, partially based on commercial off-the-shelf (COTS) components, is under development to upgrade the existing ASDEX Upgrade (AUG) broadband reflectometry diagnostic so that a full demonstration of plasma position control using RT reflectometry density profile measurements can be performed. The 8-channel (12-bit/100 MSPS) DAS being designed features a PCI Express (PCIe) x8 interface to enable direct memory access (DMA) data transfers with throughputs in excess of 1 GB/s. The use of COTS components resulted in a faster hardware design cycle without compromising system performance and flexibility. The architecture of the system and its main design constraints as well as the system integration in the AUG RT diagnostic network are herein discussed. Preliminary benchmark results for data throughput and overall measurement latency are also presented.

As digital systems grow rapidly in complexity and sophistication, the educational process must provide future developers with experience that incorporates advanced development tools and modem design techniques. However, this cannot be achieved at the expense of relevant theory and traditional design methods on which modem methods are based. Hence, the learning experience must efficiently combine emphasis on classical design principles with an exposure to state-of-the-art tools and techniques. This student project demonstrates the use of hardware description language design with programmable logic devices to develop a digital system of significant complexity, while introducing the basic principles of spread spectrum communications. After 20 years, this latter technology still remains a modern digital approach to reliable communications, and provides a practical and challenging educational application. This paper summarizes the design and full system hardware implementation of a baseband digital direct sequence spread spectrum communication system for classroom demonstration. The system configuration includes a serial transmitter with pseudorandom spreading routine, a receiver with despreader, and other diagnostic equipment.

The book contains the theory of discrete communication systems that are presented in the form of block schematics defined by mathematical operators. For the sake of comparison, the theory of digital communication systems is added to understand better the relations between the two theories. Two generic schemes of the systems are designed that are used to develop specific discrete and digital systems as their special cases. The complementary chapters of the book contain the theory of the continuous time and discrete-time processing of the deterministic and stochastic signal that is necessary for understanding the main chapters presenting communication systems.