Research on metastability based on FPGA

With the high-speed development of integrated circuits, digital systems are growing in size and complexity. In complex digital systems, different modules may run under different clock domains. For example, in a communication system, the data receiving module and the data processing module may be driven by different clocks, where it requires an effective data caching mechanism to coordinate data transfer between different clock domains. Asynchronous FIFO meets this need. It can securely store and transfer data between different clock domains, reducing the possibility of data loss and errors. This paper gives a comprehensive review of the design of asynchronous FIFO, and summarizes the characteristics and advantages of asynchronous FIFO in a metastable state, empty-full signal creation, low latency, high throughput, parameterizable design, and the performance of different design methods and application scenarios by analyzing several related research results. The purpose is to provide a reference for further research and application of asynchronous FIFO.

Electronic systems are being designed with increasing levels of digital logic integration, quite often in the form of digital application specific integrated circuits (ASICs). The level of integration in these devices (10000 to greater than 100000 primitive logic elements such as "gates" and/or flip flops) presents a difficult challenge to design engineers for the development of a comprehensive set of test vectors to verify that all of the elements within the ASIC operate correctly. The percentage of possible logic elements (gates, flip flops, etc.) tested by the test vectors is known as fault coverage (FC). Although 100% fault coverage is a desired goal, quite often the complexity of the ASICs preclude reaching that goal. The hazards of insufficient fault coverage are magnified in complex systems with many ASICs, for if an untested defective logic element were to be exercised in any one ASIC, a system failure would occur. This paper presents a mathematical model to develop digital ASIC fault coverage guidelines for complex electronic systems. The model is based on established probabilistic relationships between integrated circuit fabrication yields, fault coverage and the resulting device defect level, combined with an estimated probability that untested logic elements will be exercised in use. The results of this model can be used to allocate the ASIC fault coverage requirements necessary to achieve high system mission success rates.

BTI, HCI and TDDB aging impact in flip–flops

Usually complex systems are controlled by an operator co-operating with a computer-based controller. The controlling software runs in continuous interaction with the operator and constantly reacts on operator’s interruptions by dynamically adapting system behaviour. Simultaneously it catches the exceptions signalling about errors in the system components and performs error recovery. Since interruptions are asynchronous signals they might concurrently co-exist and conflict with exceptions. To ensure dependability of a dynamically adaptable system, we propose a formal approach for resolving conflicts and designing robust interruption and exception handlers. We present a formal specification pattern for designing components of layered control systems that contain interruption and exception handlers as an intrinsic part of the specification. We demonstrate how to develop a layered control system by recursive application of this pattern.

Flexible behaviors are organized by complex neural networks in the prefrontal cortex. Recent studies have suggested that such networks exhibit multiple dynamical states, and can switch rapidly from one state to another. In many complex systems such as the brain, the early-warning signals that may predict whether a critical threshold for state transitions is approaching are extremely difficult to detect. We hypothesized that increases in firing irregularity are a crucial measure for predicting state transitions in the underlying neuronal circuits of the prefrontal cortex. We used both experimental and theoretical approaches to test this hypothesis. Experimentally, we analyzed activities of neurons in the prefrontal cortex while monkeys performed a maze task that required them to perform actions to reach a goal. We observed increased firing irregularity before the activity changed to encode goal-to-action information. Theoretically, we constructed theoretical generic neural networks and demonstrated that changes in neuronal gain on functional connectivity resulted in a loss of stability and an altered state of the networks, accompanied by increased firing irregularity. These results suggest that assessing the temporal pattern of neuronal fluctuations provides important clues regarding the state stability of the prefrontal network. We also introduce a novel scheme that the prefrontal cortex functions in a metastable state near the critical point of bifurcation. According to this scheme, firing irregularity in the prefrontal cortex indicates that the system is about to change its state and the flow of information in a flexible manner, which is essential for executive functions. This metastable and/or critical dynamical state of the prefrontal cortex may account for distractibility and loss of flexibility in the prefrontal cortex in major mental illnesses such as schizophrenia.

Aim. Interoception reflects the perception, integration and modulation of visceral signals. Currently, there is no established universal approach to cardiac interoception assessment allowing its inclusion in the diagnostic protocol for various diseases. The aim was to compare three tests of interoception self-assessment based on heart palpitations within one day in healthy subjects.Material and methods. Eighty healthy volunteers took part in the study. To assess cardiac interoception, a test with button pushes at the moment of palpitations, a feedback test in the form of synchronous and asynchronous sound signals, a heartbeat counting task at specified time intervals were conducted with simultaneous electrocardiographic recording. The obtained data were compared with each other (Wilcoxon test). Its pairwise dependence (Spearman coefficient) and dependence on body parameters (sex, age, body mass index, fat mass, anxiety) were assessed (univariate linear regression).Results. The accuracy of the heartbeat counting task turned out to be significantly higher than in the button- pressing test (p=0,005). However, both estimates correlate with each other (r=0,66, p=0,003). A positive dependence of test accuracy on sex was found for the heartbeat counting task (p=0,021) and a negative dependence on fat mass for button- pressing task (p=0,032).Conclusion. The study found that volunteers' estimates of heartbeat accuracy varied across tests and were also associated with sex and body composition. The heart rate counting task and the button- pressing task are the most suitable for interoception assessment.

A small-size on-chip capacitively coupled 4-channel direction-configurable digital isolator in standard 0.18 μm CMOS technology is proposed. The isolation element area is 1/20-1/4 that of transformer-based isolator. Transmitter (TX) and receiver (RX) dies, each of which has isolation capacitors, are connected together within a standard IC package and communicate through isolation barrier. The on-off keying (OOK) transmitter consists of a threshold matched high speed Schmitt trigger for better signal synchronization between different channels. An envelop-detection RX is proposed to achieve high noise immunity. Post simulation shows that the proposed architecture achieves 200 Mbps data rate, 6 ns small propagation delay, 6.4 mA power consumption per channel when transmitting 100 Mbps data and 100 kV/μ s common-mode rejection (CMR).

As future manned and robotic space explorations missions involve more complex systems, it is essential to verify, validate, and optimize such systems through simulation and emulation in a low cost testbed environment. The goal of such a testbed is to perform detailed testing of advanced space and ground communications networks, technologies, and client applications that are essential for future space exploration missions. We describe the development of new technologies enhancing our Multi-mission Advanced Communications Hybrid Environment for Test and Evaluation (MACHETE) that enable its integration in a distributed space communications testbed. MACHETE combines orbital modeling, link analysis, and protocol and service modeling to quantify system performance based on comprehensive considerations of different aspects of space missions. It can simulate entire networks and can interface with external (testbed) systems. The key technology developments enabling the integration of MACHETE into a distributed testbed are the Monitor and Control module and the QualNet IP Network Emulator module. Specifically, the Monitor and Control module establishes a standard interface mechanism to centralize the management of each testbed component. The QualNet IP Network Emulator module allows externally generated network traffic to be passed through MACHETE to experience simulated network behaviors such as propagation delay, data loss, orbital effects and other communications characteristics, including entire network behaviors. We report a successful integration of MACHETE with a space communication testbed modeling a lunar exploration scenario. This document is the viewgraph slides of the presentation.

In LTE(Long-Term Evolution) system, UE(User Equipment) performs synchronization processing with a specific cell to communicate. In that processing, the UE uses a matched filter to filter PSS(Primary Synchronization Signal) from downlink signals sent from the cell. There are various ways to design such a matched filter. In the most native design of the matched filter, the number of multipliers is required as much as a number of the taps which means filter length. If resources are limited, that is a very inefficient design approach. Therefore, we proposed filter design method to significantly reduce the number of multipliers in the matched filter by utilizing the difference of between sampling rate and operating clock frequency. When using FPGA resources for designing the filter, The filter design method proposed in this paper reduced the LUT(look-up table) utilization by 55.2% to 6.22%, the FF(flip-flop) utilization decreased by 24.95% to 4.44%, and the BRAM utilization decreased by 42.65% to 13.05% than the Natively design method.

Synchronization using flip-flop chains imposes a latency of a few clock cycles when transferring data and control signals between clock domains. We propose a design scheme that avoids this latency by performing synchronization as part of state/data computations while guaranteeing that metastability is contained and its effects tolerated (with an acceptable failure probability). We present a theoretical framework for modeling synchronous state machines in the presence of metastability and use it to prove properties that guarantee some form of reliability. Specifically, we show that the inevitable state/data corruption resulting from propagating metastable states can be confined to a subset of computations. Applications that can tolerate certain failures can exploit this property to leverage low-latency and quasi-reliable operation simultaneously. We demonstrate the approach by designing a Network-on-Chip router with zero-latency asynchronous ports and show via simulation that it outperforms a variant with two flip-flop synchronizers at a negligible cost in packet transfer reliability.

S12EXAMINATION OF STARTLE-ASSOCIATED GENES AND THE CHANGE IN ANXIETY SYMPTOM SEVERITY FOLLOWING PHARMACOLOGICAL TREATMENT

The paper considers the problem of ensuring trouble-free operation of technological equipment operating in automatic mode, using the example of a pneumatic cylinder assembly line. It is shown that with the increasing complexity of automated systems, increasing speed and increasing the number of operations performed without the participation of the operator, the requirements for equipment reliability, accuracy of mutual positioning of elements and timely detection of emergency and pre-emergency states are significantly increasing. Particular attention is paid to operations of precision connection of critical structural elements, which are characterized by errors in the form of misalignment, skew of axes and inconsistency of spatial orientation of parts, which can lead to a decrease in the resource of mechanisms or equipment failure. An approach to organizing test and step-by-step modes of operation of an automatic control system is proposed, which allows for phased control of the execution of technological operations, identification of positioning errors and failures of actuators without the system going into emergency mode. The principles of constructing an asynchronous control machine using typical pneumatic cylinder control modules, as well as mechanisms for time synchronization of control and feedback signals, are considered. The structure of a typical control module is presented, which ensures coordination of external asynchronous signals with internal clock synchronization and implements control of the permissible time for performing technological operations. The proposed technical and algorithmic solutions increase the reliability of automatic assembly lines, ensure timely detection of failures, reduce the likelihood of emergency situations and create the prerequisites for the implementation of intelligent diagnostic and protection systems for modern technological equipment.

A multiple supply voltage scheme is an emerging approach to reduce power dissipation. The scheme requires a level converter as a bridge for different voltage domains. Conventional level converters fail to work in sub-threshold region due to the pull-down devices and the pull-up devices operate in sub-threshold and super-threshold region respectively. By employing diode-connected PMOS transistors, multiple-threshold-voltage CMOS (MTCMOS), and stack leakage reduction techniques, the proposed cross-coupled level converter achieves small propagation delay, low power consumption, and best power-delay-product (PDP) performance. Also, the reverse short channel effect is utilized to provide our level converter better process/thermal variation immunity. We also propose a dual edge-triggered explicit-pulsed level-converting flip flop (LCFF) concept combining a DCVSPG latch and our level converter. The proposed cross-coupled level converter is designed using TSMC 65nm bulk CMOS technology. It functions correctly across all process corners for a wide input voltage range, from 150mV to 1V. The level converter has a propagation delay of 52ns and a power dissipation of 21nW when the input voltage is 150mV.

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We present a phenomenological model for the dynamics of disordered (complex) systems. We postulate that the lifetimes of the many metastable states are distributed according to a broad, power law probability distribution. We show that aging occurs in this model when the average lifetime is infmite. A simple hypothesis leads to a new functional fornl for the relaxation which is in remarkable agreement with spin-glass experiments over nearly five decades in time. In spite of fifteen years of dispute, the theory of equilibrium spin-glasses is not yet settled (1, 2, 3). Dynamical effects are, however, likely to be the dominant aspect in experiments. One of the most striking aspects of the dynamics of spin-glasses in their low temperature phase is the aging phenomenon- a rather peculiar and awkward feature from the thermodynamics point of view : the relaxation of a system depends on its history. More precisely, if a system is field-cooled below its spin-glass temperature, the magnetization relaxation depends on the Waiting time t~ between the quench and the switch off of the magnetic field (4, 5, 6). Similar effects are observed on the viscoelastic properties of polymer melts (7), magnetic properties of HTC superconductors (8) and more recently on the relaxation after a heat pulse in Charge Density Wave systems (9). Analytical fits of the magnetization relaxation as a function of time have been proposed. In (6), it is proposed that the initial «stationary» part of the relaxation is a power-law With a small (negative) exponent. For times longer than the Waiting time, relaxation is Well fitted by a « stretched » exponential decay, provided that an effective time is introduced (6). In (4, 5), however, a stretched exponential of the «real» time was found for relatively short times. Many phenomenological theories have been devised to account for the stretched exponential decay lo-14), and for the slow part and aging (6, 15-18). We however feel that the basic mechanism underlying aging has not been fully appreciated (see however (17)) although it is, in our opinion, one of the constitutive properties of spin-glasses. The aim of this note is to suggest that aging is related to ergodicity breaking which has, in these systems, a peculiar and perhaps unexpected meaning. We find on some simple models that- according to our definition, see below « Weak » ergodicity breaking occurs in the spin-glass phase, defined as the phase Where the Edwards-Anderson parameter is non-zero. We see however no reason Why the two should be linked in general, and suggest that the appearance of aging could be