Optimization of motion estimation hardware using charged system optimization with low power multipliers for H.264 encoders

This paper presents a Charged System Search (CSS) algorithm to solve for robotic drill path optimization involved in printed circuit board (PCB) manufacturing industries. Most of the operational time of a PCB Robotic Drill is spent on moving the drill bit between the holes. An optimized path translates to a minimal cost of operating the robot. The drill path consists of a number of potential locations where the holes are going to be drilled. As the number of holes required increases so thus does the complexity to find the optimized path. Recently developed CSS algorithm proposed to solve this complex problem with minimal computational time. The performance of CSS algorithm is tested and verified with four case studies from the literature. The computational experience conducted in this research indicates that the proposed algorithm is capable to efficiently find the optimal path for PCB holes drilling process with reasonable computational time.

Charged System Search Algorithms for Optimal Tuning of PI Controllers

Block matching algorithms (BMAs) are often employed for motion estimation (ME) in video coding. Most conventional BMAs treat the ME problem as an optimization problem and employ certain search schemes to find a solution. Except the time-consuming full search algorithms (FS), other fast algorithms such as the three step search (TSS), searching on a reduced search range, cannot guarantee optimal solutions, i.e., search is often trapped at local minima; the ME results are thus usually unsatisfactory. Few of them makes use of the information inherent in the images explicitly. We propose a new ME algorithm which can reduce the search range while guaranteeing global optimality in most cases. Microblock visual patterns are designed to extract edge information to guide block matching: searching is only carried out at places where the real match most likely happens; that is where similar edge features present. The proposed algorithm obtains a speed about 7 - 8 times as fast as that of FS with same search range. The prediction quality is very close to that of FS and much better than that of TSS. It can produce MPEG-1 or MPEG-2 compatible motion vectors, and can be extended to model-based ME. It is suitable for parallel implementation too. Moreover, the visual patterns are potential resources for video indexing to facilitate content-based information retrieval, which is important for applications such as VOD.

In this paper, two-dimensional Discrete Wavelet Transform (2-D DWT) based image compression is presented with the help of developed Enhanced square root carry select adder (ESCSLA). The Enhanced Carry select adder is replacing the RCA and BEC unit to D-latch circuit. It provides better results than compared to the conventional adders. DWT and ESCSLA circuit is designed through Very Large Scale Integration (VLSI) System design environment. Low power consumption, less area and high speed are the main concerns in VLSI System design. Hence, our aim is to reduce the hardware complexity of ESCSLA and improve the performance of DWT in terms VLSI concerns. In our work, three levels of decomposition are made for image compression. With the help of pixel values of image and Enhanced square root carry select adder circuit, 2-D DWT image compression technique is implemented through Verilog HDL design. The performance of ESCSLA circuit is better than conventional Binary to Excess1 (BEC) based Square Root Carry Select Adder (SQRT CSLA) in terms of silicon area and power consumption. Hence, the performance of DWT also increased when incorporating EHRCA circuit into addition process of DWT computation.

The growing popularity of high resolution video and the continuously increasing demands for high quality video on mobile devices are producing stronger needs for more efficient video encoder. Concerning these desires, HEVC, a newest video coding standard, has been developed by a joint team formed by ISO/IEO MPEG and ITU/T VCEG. Its design goal is to achieve a 50% compression gain over its predecessor H.264 with an equal or even higher perceptual video quality. Motion Estimation (ME) being as one of the most critical module in video coding contributes almost 50%-70% of computational complexity in the video encoder. This high consumption of the computational resources puts a limit on the performance of encoders, especially for full HD or ultra HD videos, in terms of coding speed, bit-rate and video quality. Thus the major part of this work concentrates on the computational complexity reduction and improvement of timing performance of motion estimation algorithms for HEVC standard. First, a new strategy to calculate the SAD (Sum of Absolute Difference) for motion estimation is designed based on the statistics on property of pixel data of video sequences. This statistics demonstrates the size relationship between the sum of two sets of pixels has a determined connection with the distribution of the size relationship between individual pixels from the two sets. Taking the advantage of this observation, only a small proportion of pixels is necessary to be involved in the SAD calculation. Simulations show that the amount of computations required in the full search algorithm is reduced by about 58% on average and up to 70% in the best case. Secondly, from the scope of parallelization an enhanced TZ search for HEVC is proposed using novel schemes of multiple MVPs (motion vector predictor) and shared MVP. Specifically, resorting to multiple MVPs the initial search process is performed in parallel at multiple search centers, and the ME processing engine for PUs within one CU are parallelized based on the MVP sharing scheme on CU (coding unit) level. Moreover, the SAD module for ME engine is also parallelly implemented for PU size of 32×32. Experiments indicate it achieves an appreciable improvement on the throughput and coding efficiency of the HEVC video encoder. In addition, the other part of this thesis is contributed to the VLSI architecture design for finding the first W maximum/minimum values targeting towards high speed and low hardware cost. The architecture based on the novel bit-wise AND scheme has only half of the area of the best reference solution and its critical path delay is comparable with other implementations. While the FPCG (full parallel comparison grid) architecture, which utilizes the optimized comparator-based structure, achieves 3.6 times faster on average on the speed and even 5.2 times faster at best comparing with the reference architectures. Finally the architecture using the partial sorting strategy reaches a good balance on the timing performance and area, which has a slightly lower or comparable speed with FPCG architecture and a acceptable hardware cost

An increasing number of research groups are developing custom hybrid analog/digital very large scale integration (VLSI) chips and systems that implement hundreds to thousands of spiking neurons with biophysically realistic dynamics, with the intention of emulating brainlike real-world behavior in hardware and robotic systems rather than simply simulating their performance on general-purpose digital computers. Although the electronic engineering aspects of these emulation systems is proceeding well, progress toward the actual emulation of brainlike tasks is restricted by the lack of suitable high-level configuration methods of the kind that have already been developed over many decades for simulations on general-purpose computers. The key difficulty is that the dynamics of the CMOS electronic analogs are determined by transistor biases that do not map simply to the parameter types and values used in typical abstract mathematical models of neurons and their networks. Here we provide a general method for resolving this difficulty. We describe a parameter mapping technique that permits an automatic configuration of VLSI neural networks so that their electronic emulation conforms to a higher-level neuronal simulation. We show that the neurons configured by our method exhibit spike timing statistics and temporal dynamics that are the same as those observed in the software simulated neurons and, in particular, that the key parameters of recurrent VLSI neural networks (e.g., implementing soft winner-take-all) can be precisely tuned. The proposed method permits a seamless integration between software simulations with hardware emulations and intertranslatability between the parameters of abstract neuronal models and their emulation counterparts. Most important, our method offers a route toward a high-level task configuration language for neuromorphic VLSI systems.

Block-matching algorithm is the most common technique applied in block-based motion estimation technique. There are several block-matching algorithm based on block-based motion estimation techniques have been developed. Full search (FS), three step search (TSS), new three step search (NTSS), diamond search (DS) and hexagon based search (HS) are the most well known block-matching algorithm. These techniques are applied to video sequences to remove the temporal redundancy for compression purposes and to gauge the motion vector estimation. In addition, the mentioned block-matching algorithms are the baseline techniques that have been used to further develop all the enhanced or improved algorithms. In order to develop the proposed methods, the baseline techniques are studied to develop the proposed algorithms. This chapter proposes modelling of fast unrestricted hexagon search (FUHS16) and unrestricted hexagon-diamond search (UHDS16) algorithms for motion vector estimation, which is based on the theory and application of block-based motion estimation. Both of these algorithms are designed using 16 × 16 block size. In particular, the motion vector estimation, quality performance, computational complexity, and elapsed processing time are emphasised. These parameters have been used to measure the experimental results. It is the aim of this study that this work provides a common framework with which to evaluate and understand block-based matching motion estimation performance. On the theoretical side, four fundamental issues are explored: (1) division of frame, (2) basic block-based matching, (3) motion vector estimation, and (4) block-matching algorithm development. Various existing block-matching motion estimation algorithms have been analysed to develop the fundamental research. Based on the theoretical and fundamental research analysis the FUHS16 and UHDS16 algorithms using 16 × 16 block-based motion estimation formulations were developed. To improve the UHDS16 algorithm, 8 × 8 block-matching technique has been tested. The 8 × 8 block-matching technique is known as UHDS8. The results show positive improvements. From an application perspective, the UHDS8 algorithm efficiently captured the motion vectors in many video sequences. For example, in video compression, the use of motion vectors on individual macro-blocks optimized the motion vector information. The UHDS8 algorithm also offers improvement in terms of image quality performance, computational complexity and elapsed processing time. Thus, this chapter offers contributions in certain areas such as reducing the mechanism of computational complexity in estimating the motion from the video sequences. In particular, the FUHS16, UHDS16 and UHDS8 algorithms were developed to estimate the motion vectors field in the video sequences. Theoretical analysis block-based matching criteria are adapted to FUHS16, UHDS16 and UHDS8 algorithms, which are based on search points technique. Basically, the proposed of FUHS16, UHDS16 and UHDS8 algorithm produces the best motion vector estimation finding based on the block-based matching criteria. Besides that, the UHDS8 algorithm also improves the image quality performances and the search points in terms of the computational complexity. Overall, the study shows that the UHDS8 algorithm produces better results compared to the FUHS16 and UHDS16 algorithm.

Motion estimation is the process which generates the motion vectors that determine how each motion compensated prediction frame is created from the previous frame. But its computational complexity poses great challenges for real time implementations. Among the different motion Estimation algorithms block matching motion estimation is the most common method of motion estimation. To minimize the search time on block matching, a simplified and efficient algorithm is very crucial for fast motion estimation process. In this paper the comparative performance of 6 different block matching algorithms are presented and compared based on the parameters of Peak Signal Noise Ratio (PSNR), Mean Absolute Difference (MAD) and Search Points per Macro block.

Using cutting-edge 32 nm Carbon Nanotube Field-Effect Transistor (CNTFET) technology, a unique 8-transistor full adder is suggested for very large scale integration (VLSI) systems. This design attempts to solve the difficulties of scaling conventional complementary metal-oxide-semiconductor (CMOS) based adders into nanoscale technology while striking a balance between power consumption, physical size, and operational speed. In HSPICE simulations, the design exhibits a fast propagation delay of 5.55 × 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−11</sup> seconds while maintaining performance across latency, power consumption, and energy efficiency with a low transistor count. This delay is constant over a broad supply voltage range (0.7 V to 1.5 V). In comparison to current designs like HFA26, CMOS28, and 9T adders, the average power consumption is still low, and the PDP and EDP values are good. Additionally, steady power and delay performance under realistic thermal circumstances is confirmed by temperature change studies. Monte Carlo analysis confirms that the design is resilient to changes in the process. The suggested 8T full adder is a promising option for next nanoscale and low-power VLSI applications since it provides a small, low-power, and energy-efficient solution.

In a synchronous digital system, the clock signal is used to define a time reference for the movement of data within that system. Since this function is vital to the operation of a synchronous system, much attention has been given to the characteristics of these clock signals and the networks used in their distribution. Clock signals are often regarded as simple control signals; however, these signals have some very special characteristics and attributes.Clock signals are typically loaded with the greatest fanout, travel over the greatest distances, and operate at the highest speeds of any signal, either control or data, with in the entire synchronous system. Since the data signals are provided with a temporal reference by the clock signals, the clock waveforms must be particularly clean and sharp. Furthermore, these clock signals are particularly affected by technology scaling, in that long global interconnect lines become signicantly more resistive as line dimensions are decreased. This increased line resistance is one of the primary reasons for the increasing significance of clock distribution on synchronous performance. Finally, the control of any differences and uncertainty in the arrival times of the clock signals can severely limit the maximum performance of the entire system and create catastrophic race conditions in which an incorrect data signal may latch within a register.Most synchronous digital systems consist of cascaded banks of sequential registers with combinatorial logic between each set of registers. The functional requirements of the digital system are satisfied by the logic stages. The global performance and local timing requirements are satisfied by the careful insertion of pipeline registers into equally spaced time windows to satisfy critical worst case timing constraints. The proper design of the clock distribution network ensures that these critical timing requirements are satisfied and that no race conditions exist.The delay components that make up a general synchronous system are composed of the following three individual subsystems: the memory storage elements, the logic elements, and the clocking circuitry and distribution network. Interrelationships among these three subsystems of a synchronous digital system are critical to achieving maximum levels of performance and reliability.Novel structures are currently under development to ameliorate these issues and provide effective solutions. Important area of research include resonant clocking techniques, on-chip optical interconnect, and local synchronization methodologies.The literature in this field exists in a variety of journals and conference proceedings. Examples include the IEEE Transactions of Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, the IEEE/ACM Design Automation Conference, and a host of related computer, circuits, and CAD conferences. Survey and review articles exist that summarize many of the primary results while providing background and perspective.

Reliability of majority voting based VLSI fault-tolerant circuits : Charles E. Stroud. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2, 4, 516 (December 1994)

An overview of the problems in generating a synchronous clock signal for electrical very large scale integration (VLSI) and multi-processor systems is given. Alternative clocking schemes using optical distribution techniques are then presented and compared with the electrical methods. Issues related to holographic signal distribution are discussed in detail.

A real-time clustering microchip neural engine : Teresa Serrano-Gotarredona and Bernabe Linares-Barranco. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1996, 4(2), 195

Cumulative balance testing of logic circuits : KRISHENDU CHAKRABARTY and JOHN P. HAYES. IEEE Transactions on Very Large Scale Integration (VLSI) System, 3(1), 72 (March 1995)

A novel GaAs logic family, pseudodynamic latched logic (PDLL), is presented in this paper. It is composed of a dynamic circuit where the logic is performed and a static latch whose function is to permanently refresh the stored data on a dynamic node. Because of this hybrid structure, PDLL takes advantage of both static and dynamic families and thus, permits implementation of very complex structures with good speed-area power tradeoff. Moreover, the inclusion of the latch permits this class of logic family to be highly efficient for pipelined systems working even at high temperature without loss of data due to leakage currents. Barrel-shifters, programmable logic arrays (PLA's), and carry lookahead adders (CLA's) were verified by simulations demonstrating its feasibility for the development of high-performance very large scale integration (VLSI) systems.