Optimized hardware implementation of the advanced encryption standard algorithm

The Consultative Committee for Space Data Systems (CCSDS) recommends AES algorithm as a cryptographic algorithm to maintain confidentiality and data security between spacecraft and ground systems. In implementation, there are several AES algorithm operating modes including Cipher-Block Chaining (CBC), Electronic Codebook (EBC), Cipher Feedback (CFB), Output Feedback (OFB), and counter mode (CTR). One of the operating modes of AES algorithm recommended by CCSDS is CTR because it has advantages in terms of efficiency of implementation and offers a high level of data security. LAPAN-A4 as the next generation of LAPAN satellites also uses CCSDS standard in terms of data exchange between satellites and ground stations including telemetry and telecommand (TTC) data and satellite payload data. In order to protect LAPAN-A4 satellite data, especially TTC data, in this paper AES algorithm was implemented in CTR operating mode on the FPGA which will then be implemented on LAPAN-A4 satellite onboard data handling (OBDH) as one of LAPAN-A4 satellite data security systems. To overcome the limited resource of FPGA, optimization is also done using basic iterative AES hardware reused method, which is to reuse hardware that has been designed n times for same operation for AES algorithm. From the results of implementation and optimization, efficiency of logic gates used is increasing almost a quarter less than the previous research.

This study discusses the effectiveness of using AES (Advanced Encryption Standard) and RC4 (Rivest Chipper 4) as digital data security algorithms to prevent and protect transaction data from irresponsible parties. This needs to be done because the development of sales transactions or other services has used digital technology a lot. This situation causes the need to secure digital data from existing transactions, so that transaction data can be stored safely. Transaction data security is carried out by changing data into ciphers or codes that are difficult to read using the AES (Advanced Encryption Standard) and RC4 (Rivest Cipher 4) algorithms. This research begins by collecting existing transaction data and then transforming it into ASCII code. The results of the transformation will be used to perform calculations using the AES algorithm. After completing the calculation process using the AES algorithm, then do the calculations using RC4. These results will be stored in the database so that the transaction data that has turned into these codes cannot be known by other parties. The combination of the AES and RC4 algorithms is carried out to strengthen data encryption because there are more and more rotation systems and double security is carried out so that digital data is not easily read and misused. With the presence of this research, it can be shown that the AES and RC4 algorithms are capable of encrypting existing transaction data with multiple levels of security.

The meaning of security is to protect something important from not authorized peoples. Cryptography is one of the security systems. Many applications could be used in the security systems like military applications, email, banking, information technology of database. The proposed system uses advanced encryption standard(AES) with secure hash algorithms(SHA-1) to produce a strong ciphertext. Moreover, this paper make the combination of (SHA-1) which is a one way encryption, as a key with (AES) algorithm which is a two way encryption as a ciphering generator to obtain confidentiality and integrity, In this paper presented implementation of Advanced Encryption Standard (AES) and Secure Hash (SHA-1) Algorithm by the use of FPGA Hardware card, However implementation of the AES algorithm and SHA-1 using LABVIEW environment with MATLAB system generator to generate stream data to FPGA hardware target. The output of the hash function is used as an input key for AES in order to improve data security, From the algorithms result of AES and SHA-1 obtained in FPGA, the system obtained how it is simple in modeling hashing and AES algorithms, generating hash codes and plain texts in (small and capital letters), symbols and numbers. The FPGA card used in this system (Spartan 3AN)with frequency (50%), the complete system take (1,147)size from the available space of (11,776) and accuracy (90%),the system work properly.

Mobile ad hoc network (MANET) is a group of mobile nodes that communicates with each other without any supporting infrastructure. These networks have some unique features such as dynamic mobility, open nature, lack of infrastructure, limited physical security and they are vulnerable to several security threats. Malicious node can drop all or partial received packets instead of forwarding them to the next hop through the path. In order to find the malicious nodes, an initial transmission is made between the source and destination nodes. Using fuzzy rules, the trust value of each node is computed and it varies from 0 to 1. A common threshold value is set for each node and by using this threshold value, every node in the network can be identified as either a malicious node or a regular node. After identifying the malicious nodes, these nodes are eliminated by muting the power to off state. As the malicious nodes are eliminated between source and destination nodes, source node can select another trusted path to its destination
 node. For security and authentication of routing information, hybrid cryptography is employed, using advanced encryption standard (AES) and elliptic curve cryptography (ECC) algorithms. AES algorithm is used as symmetric algorithm to encrypt the routing information and ECC algorithm is used as asymmetric algorithm to encrypt the public key. During encryption, the original plain text is converted into cipher text with encrypted public key and similarly during decryption cipher text is converted into original plain text with decrypted private keys. So the proposed method involves both AES and ECC algorithms which provides security mechanism as efficient and sufficient one. The experimental simulations are carried for the proposed model using network simulator 2 (NS-2) for Throughput, Delay, Packet delivery ratio, Packet overhead and Packet drop.

An efficient AES implementation using FPGA with enhanced security features

The National Institute of Standards and Technology (NIST) of US announced Rijndael algorithm as the advanced encryption standard (AES) in October 2000, Despite AES surpassing in security the data encryption standard (DES), it is still rare to be implemented in smart cards, due to the reason of deficient AES coprocessors. Here a chip operation system (COS) called NexCard, which derived from Microsoft's Windows COS, is used as the AES implementation platform. After a suitable COS architecture design for AES and methodology of efficient memory usage, the simulation result shows that direct embedding AES encryption attains 0.56 ms at system clock 15 MHz on the INFINEON SLE66CX322P chip without existence of coprocessor. Corresponding to the development needs in smart card cryptographic algorithm implementations, and different level of the security design specifications, a concept to conjoin numbers of algorithms into single smart card called cipher system on demand (CSOD) method is accomplished in this study concurrently. This is a method utilizing the multiapplication capability of NexCard v2.0 to execute the same AES algorithm as an on-card applet. Although the performance of CSOD is not as good as AES embedded method, CSOD can provide the same result in the situation of adaptability and extendibility.

With the rapid development of internet technology and the increasing popularity of e-commerce, data encryption technology plays a very important role in data security. Information security has two aspects: security protocol and cryptographic algorithm and the latter is the foundation and core technology of information security. Advanced Encryption Standard (AES) encryption algorithm is one of the most commonly used algorithms in symmetric encryption algorithms. Such algorithms face issues when used in the context of key management and security functions. This paper focuses on the systematic analysis of these issues and summarizes AES algorithm implementation, comprehensive application and algorithm comparison with other existing methods. To analyze the performance of the proposed algorithm and to make full use of the advantages of AES encryption algorithm, one needs to reduce round key and improve the key schedule, as well as organically integrate with RSA algorithm. Java language is used to implement the algorithm due to its large library, then to show the efficiency of the proposed method we compare different parameters, such as encryption/decryption speed, entropies and memory consumption...) with a classic algorithm. Based on the results of the comparison between AES and the hybrid AES algorithm, the proposed algorithm shows good performance and high security. It therefore can be used for key management and security functions, particularly for sharing sensitive files through insecure channel. This analysis provides a reference useful for selecting different encryption algorithms according to different business needs.

E-commerce becomes an electronic media that uses a login system used by users. User data in the form of usernames and passwords is vulnerable to hacking. One technique to improve user security is the implementation of AES algorithms on login systems in E-Commerce applications. The purpose of this study is to apply the AES algorithm in the login system of e-commerce websites and analyze the improvement of information security for users after the implementation is carried out. The research method used is an experiment with the application of the use of the AES algorithm before and after. Therefore, the application of the AES algorithm on the login system of e-commerce websites can be used as a solution to improve user data security. Testing using Wireshark and Burpsuite tools. The results obtained are that AES successfully secures the username and password on the e-commerce login system .

The rapid The main problem in the misuse of data used in crime is the result of a lack of file security. This study proposes a data security method to protect document files using the Advanced Encryption Standard (AES) algorithm combined with the Vigenere Cipher. This research carried out 2 processes, namely the encryption process and the decryption process. The encryption process will be carried out by the AES algorithm and then encrypted again with the Vigenere Cipher algorithm. The experiments show that the proposed method can encrypt files properly, where there are changes in the value of the document file and the encrypted file cannot be opened and the description results do not cause changes to the original file. The results of this study are that the system is able to work properly so as to produce file encryption and decryption using the AES method combined with the Vigenere Cipher. In document files, the largest difference in encryption and decryption time is 8 seconds, while in image files the difference in encryption and decryption time is 17 seconds. This longest time difference is generated by large files.

The throughput of WPAN (Wireless Personal Area Network) based on Bluetooth was decided by the interference of Bluetooth piconets in the network. The interference was decided by the hamming correlation of Bluetooth FH (Frequency Hopping) selected sequence. In order to improve the WPAN throughput, the WPAN model and data packet collision model were built and the relations about WPAN throughput, the maximum hamming correlation of FH selected sequence, the numbers of Bluetooth piconets and the SNR of channel were analyzed. The functions of WPAN throughput were deduced. After analyzing the performance of Bluetooth FH selected sequence, the original algorithm was replaced by the AES (Advanced Encryption Standard) algorithm. The theoretical analysis proved that the AES FH sequences selected algorithm could improve the WPAN throughput. The simulation results proved the theoretical analysis. The test result with ARM926EJs SoC (System on Chip) + RF (Radio Frequency) chip nRF2401 and CSR's Bluecore4 Bluetooth module got the same conclusion. All of these could prove that the AES algorithm can improve the WPAN throughput efficiently.

Human brain known commonly as an individual's computer is one of the complex organs in the body. The brain serves to control and coordinate the mental and physical actions. It has the capacity to store innumerable data. This data includes not only childhood memories but also those related to the present age. Tracking the electrical potentials or impulses, commonly known as brain waves, can be utilized for various purposes ranging from diagnosing diseases to decoding personality traits. This can be done using the technique of Electroencephalography (EEG). The amount of data available is exploding so also the opportunities of data mining thereby mounting privacy risks. The current practice either prevents the reuse of raw EEG signals or disrespects participants' right to privacy by using this data for purposes other than those consented to, by the individual. The aim of this work is to put a stop to such privacy risks by extracting and transferring only those features related to an application. Feature is a specific characteristic measurement of a pattern segment. EEG signal processing pertains mainly to feature extraction. There are different methods for extracting features from EEG signals. In this work, the features related to neurological diseases, namely epilepsy and Alzheimer's disease, are extracted using Discrete Wavelet Transform (DWT) and those related to Schizophrenia are extracted using Autoregressive (AR) method. For securing the raw data, it is doubly encrypted using Advanced Encryption Standard (AES) algorithm and is kept under the control of each user. The proposed system thus ensures the privacy of an individual's EEG signals, and mitigates any risk that may arise if raw data is made available as such to the public.

Arithmetic coding technique is very much effective and flexible and it is evident in most of the circumstances while on the other hand AES is advanced encryption standard process which deals with changeover and permutation of data for proper security. The paper presents the security and compression of data by Arithmetic coding with AES (Advanced Encryption Standard) algorithm. Basic research is to arithmetically encode the data first, followed by encryption by using AES algorithm and then transmits the code. At the receiving end the data is decrypted and decoded to produce the user data. The paper has an advantage of encoding/decoding and compression of data both at the same time. The input data size is of 128 bits or 256 bits in AES, so the idea is to compress the data before encryption by digital arithmetic coding. The arithmetic coding and Huffman coding are very much alike in their working as they both achieve the task of compression by plummeting the average number of bits required to represent each and every symbol.

Advanced Encryption Standard (AES), which is approved and published by Federal Information Processing Standard (FIPS), is a cryptographic algorithm that can be used to protect electronic data. The AES algorithm can be programmed in software or hardware. This paper presents encryption time comparison of the AES algorithm on FPGA and computer. In the study, Verilog HDL and C programming language is used on the FPGA and computer, respectively. The AES algorithm with 128-bit input and key length 128-bit (AES-128) was simulated on Xilinx ISE Design Suite 13.3. It was observed that, the AES algorithm runs on the FPGA faster than on a computer. We measured the time of encryption on FPGA and computer. Encryption time is 390ns of AES on FPGA and 11 μs of AES on a computer.

Video steganography, a technique for embedding secret information within video sequences, has gained prominence in the domain of covert communication. By exploiting the inherent redundancy and high capacity of video data, this approach enables secure data transmission without raising suspicion. This paper delves into the intricacies of AES-based video steganography, with a particular focus on the integration of the Advanced Encryption Standard (AES) algorithm. The AES algorithm, renowned for its robust encryption capabilities, serves as a cornerstone of this steganographic approach. By encrypting the secret data prior to embedding it within the video frames, an additional layer of security is introduced, safeguarding the confidentiality of the hidden information

<span lang="EN-US">Communication among end users can be based either on wired or wireless technology. Cryptography plays a vital role in ensuring data exchange is secure among end users. Data can be encrypted and decrypted using symmetric or asymmetric key cryptographic techniques to provide confidentiality. In wireless technology, images are exchanged through low-cost wireless peripheral devices, such as radio frequency identification device (RFID), nRF, and ZigBee, that can interface with field programmable gate array (FPGA) among the end users. One of the issues is that data exchange through wireless devices does not offer confidentiality, and subsequently, data can be lost. In this paper, we propose a design and implementation of AES-128 cipher algorithm on an FPGA board for image processing through the <a name="_Hlk107307233"></a>universal asynchronous receiver transmitter (UART) protocol. In this process, the advanced encryption standard (AES) algorithm is used to encrypt and decrypt the image, while the transmitter and receiver designs are implemented on two Xilinx BASYS-3 circuits connected with a ZigBee RF module. The encrypted image uses less memory, such as LUTs (141), and also consumes less chip power (0.0291 w), I/O (0.003), block RAM (0.001 w), data, and logic to provide much higher efficiency than wired communication technology. We also observe that images can be exchanged through the UART protocol with different baud rates in run time.</span>