Parallel code generation respecting allocation

McDAS, a software environment designed to support the real-time implementation of digital signal processing (DSP) applications onto multiple processors, is described. Users program their algorithms as they would on a single processor, and McDAS automatically schedules and compiles the program onto the target multiprocessor. The scheduler maximizes the computational throughput by simultaneously considering pipelining, retiming, and parallelism while accounting for processor and memory constraints, as well as interprocessor communication delays. If the architecture is scalable or configurable, the scheduler can be invoked with different numbers of processors and multiprocessor topologies to explore various implementations. The code generator is similarly retargetable to different memory architectures and core processors. Data buffers and synchronizations are automatically inserted to ensure correct execution. The code generated can also execute the algorithms with either quasi-infinite precision or bit-true precision, allowing the algorithm designer to assess the effects of quantization and truncation. The results on a set of benchmarks are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Design automation for embedded systems comprising both hardware and software components demands for code generators integrated into electronic CAD systems. These code generators provide the necessary link between software synthesis tools in HW/SW codesign systems and embedded processors. General-purpose compilers for standard processors are often insufficient, because they do not provide flexibility with respect to different target processors and also suffer from inferior code quality. While recent research on code generation for embedded processors has primarily focussed on code quality issues, in this contribution we emphasize the importance of retargetability, and we describe an approach to achieve retargetability. We propose usage of uniform, external target processor models in code generation, which describe embedded processors by means of RT-level netlists. Such structural models incorporate more hardware details than purely behavioral models, thereby permitting a close link to hardware design tools and fast adaptation to different target processors. The MSSQ compiler, which is part of the MIMOLA hardware design system, operates on structural models. We describe input formats, central data structures, and code generation techniques in MSSQ. The compiler has been successfully retargeted to a number of real-life processors, which proves feasibility of our approach with respect to retargetability. We discuss capabilities and limitations of MSSQ, and identify possible areas of improvement.

Many advances in automatic parallelization and optimization have been achieved through the polyhedral model. It has been extensively shown that this computational model provides convenient abstractions to reason about and apply program transformations. Nevertheless, the complexity of code generation has long been a deterrent for using polyhedral representation in optimizing compilers. First, code generators have a hard time coping with generated code size and control overhead that may spoil theoretical benefits achieved by the transformations. Second, this step is usually time consuming, hampering the integration of the polyhedral framework in production compilers or feedback-directed, iterative optimization schemes. Moreover, current code generation algorithms only cover a restrictive set of possible transformation functions. This paper discusses a general transformation framework able to deal with non-unimodular, non-invertible, non-integral or even non-uniform functions. It presents several improvements to a state-of-the-art code generation algorithm. Two directions are explored: generated code size and code generator efficiency. Experimental evidence proves the ability of the improved method to handle real-life problems. 1.

Code summarization and generation empower conversion between programming language(PL) and natural language (NL), while code translation avails the migration of legacy code from one PL to another. This paper introduces PLBART, a sequence-to-sequence model capable of performing a broad spectrum of program and language understanding and generation tasks. PLBART is pre-trained on an extensive collection of Java and Python functions and associated NL text via denoising autoencoding. Experiments on code summarization in the English language, code generation, and code translation in seven programming languages show that PLBART outperforms or rivals state-of-the-art models. Moreover, experiments on discriminative tasks,e.g., program repair, clone detection, and vulnerable code detection, demonstrate PLBART’s effectiveness in program understanding. Furthermore, analysis reveals that PLBART learns program syn-tax, style (e.g., identifier naming convention), logical flow (e.g., if block inside an else block is equivalent to else if block) that are crucial to program semantics and thus excels even with limited annotations.

A parallel circuit simulator, iPRIDE, which uses a direct solution method and runs on a shared-memory multiprocessor is described. The simulator is based on a multilevel node tearing approach which produces a nested bordered-block-diagonal (BBD) form of the circuit equation matrix. The parallel solution of the nested BBD matrix is described. Its efficiency is shown to depend on how the circuit is partitioned as well as the sequence in which the concurrent tasks (scheduling) are solved. A partitioning heuristic is proposed, assuming that an arbitrary number of processors is available. Scheduling methods are studied when the number of processors is fixed. A method for determining the optimal level of partitioning, which depends on the number of processors as well as the scheduling methods, is described. The program is implemented on an ALLIANT FX/8 multiprocessor with shared memory. The performance of the program is reported. >

This paper studies a number of different techniques that can be used to reduce the amount of time needed to run block diagram simulations. The first is automatic code generation techniques used to create simulation exe cutables from graphical block diagram models. A number of alternative techniques are studied, highlighting increases in simulation speed that can be achieved at the expense of intera ctivity with the graphical model. This paper will discuss at which stages of modeling and simulation code generation should be considered. The second technique that is studied is the use of computing clusters to distribute a number of simulation runs across a number of processors. With the advent of the multicore processor this technique has become a ccessible to many more engineers than in the past.

Object constraint language for code generation from activity models

Nearly all personal computer and workstation processors, and virtually all high-performance embedded processor cores, now embody instruction level parallel (ILP) processing in the form of superscalar or very long instruction word (VLIW) architectures. ILP processors put much more of a burden on compilers; without heroic compiling techniques, most such processors fall far short of their performance goals. Those techniques are largely found in the high-level optimization phase and in the code generation phase; they are also collectively called instruction scheduling. This paper reviews the state of the art in code generation for ILP parallel processors. Modern ILP code generation methods move code across basic block boundaries. These methods grew out of techniques for generating horizontal microcode, so we introduce the problem by describing its history. Most modem approaches can be categorized by the shape of the scheduling region. Some of these regions are loops, and for those techniques known broadly as are used. Software Pipelining techniques are only considered here when there are issues relevant to the region-based techniques presented. The selection of a type of region to use in this process is one of the most controversial questions in code generation; the paper surveys the best known alternatives. The paper then considers two questions: First, given a type of region, how does one pick specific regions of that type in the intermediate code. In conjunction with region selection, we consider region enlargement techniques such as unrolling and branch target expansion. The second question, how does one construct a schedule once regions have been selected, occupies the next section of the paper. Finally, schedule construction using recent, innovative resource modeling based on finite-state automata is then reexamined. The paper includes an extensive bibliography.

Advances in the areas of hardware technology, processor organization and programming science have given fresh impetus to research in parallel processing within single job streams. Given a program with a large degree of inherent parallelism, the theoretical time required for problem solution can be reduced “by a factor at least as great as the number of processors” [1].A need exists for new techniques for detecting parallel processable segments in sequentially coded programs and for indicating (representing) parallelism during actual program writing and coding. In a companion paper [4], the authors considered some methods of detecting and representing parallel processable “subtasks” within a task (process). In this paper we shall study the techniques of recognizing and representing parallel processable tasks within a single job stream (program).

SIMD instructions are often implemented in modern multimedia oriented processors. Although SIMD instructions are useful for many digital signal processing applications, most compilers do not exploit SIMD instructions. The difficulty in the utilization of SIMD instructions stems from data parallelism in registers. In assembly code generation, the positions of data in registers must be noted. A technique of generating pack instructions which pack or reorder data in registers is essential for exploitation of SIMD instructions. This paper presents a code generation technique for SIMD instructions with pack instructions. SIMD instructions are generated by finding and grouping the same operations in programs. After the SIMD instruction generation, pack instructions are generated. In the pack instruction generation, Multi-valued Decision Diagram (MDD) is introduced to represent and to manipulate sets of packed data. Experimental results show that the proposed code generation technique can generate assembly code with SIMD and pack instructions performing repacking of 8 packed data in registers for a RISC processor with a dual-issue coprocessor which supports SIMD and pack instructions. The proposed method achieved speedup ratio up to about 8.5 by SIMD instructions and multiple-issue mechanism of the target processor.

Computer software is key part of information system (IS). One of the main targets of Model-Driven Software Engineering (MDSE) is the increase in productivity and reliability offered by automatically generating code from models. However, the practical adoption of code generation remains relatively slow and limited to niche applications. A potential is to develop automated code generation and automatic model transformation. To answer the challenge, this paper proposes, based on the practicable formal methods (PAR method), the methodology for implementing formal model-driven engineering (FMDE), then to develop platform of code generation based on FMDE, called PAR Platform. We call PAR method and PAR platform as PAR. PAR consists of requirement modeling language SNL (meta-model), algorithm modeling language Radl, abstract program modeling language Apla, a set of rules for the model transformation and a set of automatic transformation tools. The tools can implement several transformations from requirement to algorithm models, then to abstract program models and finally to executable programs. The goal of the transformations is to generate executable program. There are two kinds of applications of PAR platform. One is automatic generation of many nontrivial algorithms and programs. Another is, according to FMDE, development of several safety-critical information systems.

This paper is concerned with the grain-size problem; how can we partition a program into tasks (concurrent modules) for parallel processing. Multiprocessor scheduling problem has long been studied by a number of researchers, and several scheduling algorithms have also been proposed. However, the effect of parallel processing strictly attributes of the given tasks such as the topology of task graph (directed acyclic graph representing precedence relations among tasks) and the balance of grain-size (computational time of each task) as well as the available number of processors. In order to improve the solution of multiprocessor scheduling problem, this paper proposes an excellent method for restructuring a given task graph. Analyzing the topology of the task graph, adequate tasks are divided one by one for increasing the parallelism of the task graph. The effect of task division is evaluated by scheduling tasks, where communication delays between distinct processors are considered. As a result, an appropriate task graph could be derived from the initially given task graph with respect to the designated number of processors. The proposed method is successfully applied to the parallel processing of robot-arm control computation on a multiprocessor system.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The design of a Multiprocessor System-on-Chip (MPSoC) is a complex task, including steps as application development, platform configuration, code generation, task mapping onto the platform and debugging. An integrated environment covering most of these steps is a gap in the literature. The present work first details an MPSoC architecture, which supports the execution of distributed applications, including an operating system enabling multitask execution at each processing element. The MPSoC is heterogeneous, due to the support to different processor architectures. Then, a framework able to cover the design steps previously mentioned is presented. The framework enables the design space exploration for applications to be executed in the MPSoC, varying for example the number and type of processors, the memory size, the task mapping. Results demonstrate the correct operation for different MPSoC configurations, generated from the proposed framework. Such open-source framework enables the research community to investigate new subjects related to MPSoC and Network on Chip (NoC) design, as well as evaluate distributed applications in a multiprocessor environment.

The code synthesis, especially the multi-task code generation, plays an important role in the implementation of the safety-critical applications. MiniSIGNAL is a sequential/multi-task code generation tool for the synchronous language SIGNAL. During the application of real-world industrial case study, we find the generated programs is still inefficient due to a shortage of the original code generation strategies. Therefore, this paper presents a new multi-task code generation method for SIGNAL. Starting at the level of synchronous clocked guarded actions (S-CGA) which is an intermediate language for the compilation process of MiniSIGNAL, the transformation consists of two levels: At the platform-independent level, transforming the S-CGA code to an abstract multi-task structure (called VMT) with formal syntax and semantics; At the platform-dependent level, adopting the thread pool pattern to implement parallel Ada code generated from the VMT structure. The approach is applied to a real-world Guidance, Navigation and Control system to show the effectiveness of our approach.

This paper presents an efficient compilation technique to generate the local memory access sequences for block-cyclically distributed array references with affine subscripts in data-parallel programs. For the memory accesses of an array reference with affine subscript within a two-nested loop, there exist repetitive patterns both at the outer and inner loops. We use tables to record the memory accesses of repetitive patterns. According to these tables, a new start-computation algorithm is proposed to compute the starting elements on a processor for each outer loop iteration. The complexities of the table constructions are O(k+s/sub 2/), where k is the distribution block size and s/sub 2/ is the access stride for the inner loop. After tables are constructed, generating each starting element for each outer loop iteration can run in O(1) time. Moreover, we also show that the repetitive iterations for outer loop are Pk/gcd(Pk,s/sub 1/), where P is the number of processors and s/sub 1/ is the access stride for the outer loop. Therefore, the total complexity to generate the local memory access sequences for a block-cyclically distributed array with affine subscript in a two-nested loop is O(Pk/gcd/(Pk,s/sub 1/)+k+s/sub 2/).