IPRIDE: a parallel integrated circuit simulator using direct method

This paper discusses the development of a parallel SPICE circuit simulator using the direct method on a cloud-based heterogeneous cluster, which includes multiple HPC compute nodes with multi-sockets, multicores, and GPUs. A simple model is derived to optimally partition the circuit between the compute nodes. The parallel simulator is divided into four major kernels: Partition Device Model Evaluation (PME), Partition Matrix Factorization (PMF), Interconnection Matrix Evaluation (IME), and Interconnection Matrix Factorization (IMF). Another model is derived to assign each of the kernels to the most suitable execution platform of the Amazon EC2 heterogeneous cloud. The partitioning approach using heterogeneous resources has achieved an order-of-magnitude speedup over optimized multithreaded implementations of SPICE using state of the art KLU and NICSLU packages for matrix solution.

A parallel circuit simulator was implemented on the iPSC system. Concurrent model evaluation, hierarchical BBDF (bordered block diagonal form) reordering, and distributed multifrontal decomposition to solve the sparse matrix are used. A speedup of six times has been achieved on an eight-processor iPSC hypercube system. >

This document is intended to contain a detailed description of the mathematical formulation of Xyce, a massively parallel SPICE-style circuit simulator developed at Sandia National Laboratories. The target audience of this document are people in the role of 'service provider'. An example of such a person would be a linear solver expert who is spending a small fraction of his time developing solver algorithms for Xyce. Such a person probably is not an expert in circuit simulation, and would benefit from an description of the equations solved by Xyce. In this document, modified nodal analysis (MNA) is described in detail, with a number of examples. Issues that are unique to circuit simulation, such as voltage limiting, are also described in detail.

This paper gives a brief list of commonly used direct and indirect efficient methods for the numerical solution of optimal control problems. To improve the low accuracy of the direct methods and to increase the convergence areas of the indirect methods we suggest a hybrid approach. For this a special direct collocation method is presented. In a hybrid approach this direct method can be used in combination with multiple shooting. Numerical examples illustrate the direct method and the hybrid approach.

We describe our experiences designing and implementing a virtual PNNI network testbed. The network elements and signaling protocols modeled are consistent with the ATM Forum PNNI draft specifications. The models will serve as a high-fidelity testbed of the transport and network layers for simulation-based studies of the scalability and perforrnance of PNNI protocols. Our models are written in the new network description language TED which offers two advantages. First, the testbed design is transparent; the model descriptions are developed separately from, and are independent of, the simulation-specific code. Second, TED is compiled to run with the GTW (Georgia Tech Time Warp) simulation engine which is supported on shared-memory multiprocessors. Therefore, we directly obtain the advantages of parallel simulation. This is the first complex test of the TED modeling and simulation software system. The feedback from our experiences resulted in some significant improvements to the simulation software. The resulting PNNI models are truly transparent and the performance of the simulations is encouraging. We give results from preliminary simulations of call admission, set-up and tear-down in sample PNNI networks consisting of two hundred nodes and over three hundred edges. The time to simulate ten thousand call requests decreases significantly with the number of processors; we observe a speedup factor of 5.3 when 8 processors are employed compared to a single processor. Our initial implementations demonstrate the advantages of TED for parallel simulations of largescale networks.

A parallelizable (or malleable) task is one which can be run on an arbitrary number of processors, with a task execution time that depends on the number of processors allotted to it. Consider a system of M independent parallelizable tasks which are to be scheduled without preemption on a parallel computer consisting of P identical processors. For each task, the execution time is a known function of the number of processors allotted to it. The goal is to find (1) for each task i, an allotment of processors β, and (2) overall, a non-preemptive schedule assigning the tasks to the processors which minimizes the average response time of the tasks. Equivalently, we can minimize the flow time which is the sum of the completion times of each of the tasks. In this paper we tackle the problem of finding a schedule with minimum average response time in the special case where each task in the system has sublinear speedup. This natural restriction on the task execution time means simply that the efficiency of a task decrease or remains constant as the number of processors allotted to it increases. The scheduling problem with sublinear speedups has been shown to be NP-complete in the strong sense. We therefore focus on finding a polynomial time algorithm whose solution comes within a fixed multiplicative constant of optimal. In particular, we given algorithm which finds a schedule having a response time that is within 2 times that of the optimal schedule and which runs in O(M(M2 + P)) time.

A malleable task is a computational unit which may be executed on any arbitrary number of processors, its execution time depend- ing on the amount of resources allotted to it. According to the standard behavior of parallel applications, we assume that the mal- leable tasks are monotonic, i.e. that the execution time is decreas- ing with the number of processors while the computational work increases. This paper presents a new approach for scheduling a set of independent malleable tasks which leads to a worst case guar- antee of for the minimization of the parallel execution time, or makespan. It improves all other existing practical results includ- ing the two-phases method introduced by Turek et al. The main idea is to transfer the difficulty of a two phases method from the scheduling part to the allotment selection. We show how to formu- late this last problem as a knapsack optimization problem. Then, the scheduling problem is solved by a dual-approximation which leads to a simple structure of two consecutive shelves.

A two-sided (simultaneous) optimization technique is presented for the two-player linear quadratic Gaussian (LQG) multistage game. This direct solution method allows for further interpretation of results as compared to previously used formal solution methods. For example, this direct solution method naturally decomposes the problem into separate deterministic and stochastic terms. This decomposition provides insight into the resulting optimal control strategies. In addition to the optimal control strategies, we derive a Lagrange multiplier (influence) sequence and an expression for the performance index differential, as well as an expression for the optimal performance index value.

Fine-Grained Parallel and Distributed Spatial Stochastic Simulation of Biological Reactions

This paper examines the cost/performance of simulating a hypothetical target parallel computer using a commercial host parallel computer. We address the question of whether parallel simulation is simply faster than sequential simulation, or if it is also more cost-effective. To answer this, we develop a performance model of the Wisconsin Wind Tunnel (WWT), a system that simulates cache-coherent shared-memory machines on a message-passing Thinking Machines CM-5. The performance model uses Kruskal and Weiss's fork-join model to account for the effect of event processing time variability on WWT's conservative fixed-window simulation algorithm. A generalization of Thiebaut and Stone's footprint model accurately predicts the effect of cache interference on the CM-5. The model is calibrated using parameters extracted from a fully-parallel simulation (p=N), and validated by measuring the speedup as the number of processors (p) ranges from one to the number of target nodes (N. Together with simple cost models, the performance model indicates that for target system sizes of 32 nodes and larger, parallel simulation is more cost-effective than sequential simulation. The key intuition behind this result is that large simulations require large memories, which dominate the cost of a uniprocessor; parallel computers allow multiple processors to simultaneously access this large memory.

Performing direct simulation Monte Carlo (DSMC) calculations on parallel processors may result in a strongly unbalanced distribution of work. This situation affects the performances leading to very low speedups. We present a method which makes use of adaptive domain decomposition to dynamically distribute the computational work load. The major advantage of this method is the possibility to redistribute the fraction of work which depends on the domain decomposition only. The method has been implemented on a transputer system with up to 8 processors (20 MHz Inmos T800), using the FORTRAN version of Parasoft Express Library for parallel compilers. The problems studied were hypersonic flows of a chemically reacting gas in a two-dimensional domain. The adaptive decomposition method worked well in uniformly distributing the computational work over an arbitrary number of processors and reduced the average execution time by over the 38% in certain cases. >

This paper presents the results of an experimental study to evaluate the effectiveness of parallel simulation in reducing the execution time of gate-level models of VLSI circuits. Specific contributions of this paper include (i) the design of a gate-level parallel simulator that can be executed, without any changes on both distributed memory and shared memory parallel architectures, (ii) demonstrated speedups with both conservative and optimistic simulation protocols (almost all previous studies on circuit simulation have failed to extract speedups with conservative protocols); in particular we showed that a speedup of about 3 was obtained on 8 processors of Sparc1000 for conservative algorithms and about 2 for optimistic algorithms for circuits in the ISCAS85 benchmark suite; and (iii) performance comparison between shared memory and distributed memory implementations of the simulator.

Most of researches for large-scale parallel structural analysis using finite element method have focused on iterative solution methods since direct solution methods generally have many difficulties and disadvantages for large-scale problems. However, due to the numerical robustness of direct methods that guarantees the solution to be obtained within estimated time, direct methods are much more desirable for general application of large-scale structural analysis, as well as due to ease of use which makes most of structural engineers prefer direct methods. In this research, we propose a parallel direct solver for large-scale finite element analysis that can overcome most of difficulties and disadvantages of direct methods by using domain-wise approach for direct methods. By using the proposed solver with our own structural analysis code, we can show good scalability as a direct method and can solve the largest problem ever solved by direct solvers.

Synthetic seismogram calculation by the direct solution method : A. M. Enok, Individual Studies by Participants at the International Institute of Seismology and Earthquake Engineering, 31, 1995, pp 133–142

The development of mixed signal modelling languages such as VHDL-AMS and Verilog-A allows the behaviour of analogue and mixed signal circuits to be described at a higher level than is possible with conventional circuit-level (e.g. SPICE type) simulators. Mixed-signal simulators for these new languages can process such behavioural models far more efficiently than was previously possible. The non-linear characteristics of many circuits require differential equations to be used in the behavioural descriptions. Unfortunately, the methods used to solve these equations in a mixed-signal simulator are more computationally demanding than those required to evaluate the logic expressions used to describe digital circuits. Consequently, the simulation of analogue and mixed-signal circuits is still far less efficient than the simulation of a pure digital circuit. This paper presents an alternative approach to modelling the behaviour of analogue and mixed-signal circuits based upon piecewise linear (PWL) waveforms. Since the signals processed by these models are linearised, direct methods (i.e. non-iterative) can be used to simulate their behaviour. Several alternative methods are discussed. Examples showing the application of this approach to commonly used circuits are developed and the results compared against corresponding models written for conventional simulators. Finally, suggestions are given for implementing these techniques in a VHDL simulators. (6 pages)