Parallel gate-level circuit simulation on shared memory architectures

This paper presents the results of an experimental study to evaluate the effectiveness of multiple synchronization protocols and partitioning algorithms in reducing the execution time of switch-level models of VLSI circuits. Specific contributions of this paper include: (i) parallelizing an existing switch-level simulator such that the model can be executed using conservative and optimistic simulation protocols with minor changes, (ii) evaluating effectiveness of several partitioning algorithms for parallel simulation, and (iii) demonstrating speedups with both conservative and optimistic simulation protocols for seven circuits, ranging in size from 3K transistors to about 87K transistors.

This paper discusses the development of a parallel SPICE circuit simulator using the direct method on a cloud-based heterogeneous cluster, which includes multiple HPC compute nodes with multi-sockets, multicores, and GPUs. A simple model is derived to optimally partition the circuit between the compute nodes. The parallel simulator is divided into four major kernels: Partition Device Model Evaluation (PME), Partition Matrix Factorization (PMF), Interconnection Matrix Evaluation (IME), and Interconnection Matrix Factorization (IMF). Another model is derived to assign each of the kernels to the most suitable execution platform of the Amazon EC2 heterogeneous cloud. The partitioning approach using heterogeneous resources has achieved an order-of-magnitude speedup over optimized multithreaded implementations of SPICE using state of the art KLU and NICSLU packages for matrix solution.

A parallel circuit simulator was implemented on the iPSC system. Concurrent model evaluation, hierarchical BBDF (bordered block diagonal form) reordering, and distributed multifrontal decomposition to solve the sparse matrix are used. A speedup of six times has been achieved on an eight-processor iPSC hypercube system. >

This paper considers utilizing the popular ITA (Iterated Timing Analysis) algorithm in CSM (Combining Simulation Method) to do parallel large-scale circuit simulation. An automatic partitioning method for jobs of CSM is presented, in which the related load balancing issue is also discussed. All proposed methods have been implemented and tested. Experimental results justify pleasing effects of proposed methods.

Cycle-based simulation at register-transfer- and gate level realized by a Levelized Compiled Code (LCC) technique represents a well established method for functional verification in processor design. Due to rapidly increasing design sizes, simulation acceleration is an important issue. We present a parallel LCC simulation system that has been developed to run on loosely-coupled systems. It comprises three parallel simulators and a complex model partitioning environment. An essential idea of our parallelization approach is to valuate circuit model partitions with respect to the expected parallel simulation run-time and to integrate corresponding cost functions into partitioning algorithms. This is done on the basis of a formal model of parallel LCC simulation. In this paper, we focus on the strong relation between model partitioning and the parallel simulation technique chosen. The components of the simulation system are outlined and experimental results with respect to simulation acceleration are given for IBM processor models of different size.

During the last years, multilevel methods have been applied in parallel circuit simulation. However, aiding the convergence of multilevel methods has gained only a little notice. This paper presents a combined Newton-Raphson and Gauss-Newton (NRGN) multilevel method for parallel circuit simulation in a networked environment. The NRGN method is formulated such that convergence aiding methods can be effectively applied. The example simulations show that, especially with step-size adjusting methods, the NRGN method improves the convergence and thus the speed of parallel circuit simulation.

In this paper, we present a fully parallel transistor level full-chip circuit simulation tool with SPICE-accuracy for general circuit designs. The proposed overlapping domain decomposition approach partitions the circuit into a linear subdomain and multiple non-linear subdomains based on circuit non-linearity and connectivity. Parallel iterative matrix solver is used to solve the linear domain while non-linear subdomains are parallelly distributed into different processors topologically and solved by direct solver. To achieve maximum parallelism, device model evaluation is done parallelly. Parallel domain decomposition technique is used to iteratively solve the different partitions of the circuit and ensure convergence. Orders of magnitude speedup over SPICE is observed for sets of large-scale circuit designs on up to 64 processors.

The emergence of multi-core and many-core processors has introduced new opportunities and challenges to EDA research and development. While the availability of increasing parallel computing power holds new promise to address many computing challenges in CAD, the leverage of hardware parallelism can only be possible with a new generation of parallel CAD applications. In this paper, we propose a novel multi-algorithm parallel circuit simulation approach (MAPS) and its multi-core implementation to expedite one of the most fundamental CAD applications: transistor-level transient circuit simulation. MAPS starts multiple simulation algorithms in parallel for a given simulation task. By properly synchronizing these algorithms on-the-fly, we exploit the diversity in simulation algorithms to achieve possibly superlinear overall speedup in transient simulation. In addition, our unique multi-algorithm framework allows unique safe exploration of simulation methods that are conventionally discarded due to convergence concerns. As a coarse grained parallel simulation approach, the implementation of MAPS demands a minimum of parallel programming effort and allows for reuse of existing serial simulation codes.

This work exploits the recently developed telescopic projective numerical integration method for efficient parallel circuit simulation. Stable explicit numerical integration is achieved by adopting an explicit inner integrator (e.g. forward Euler) in a multi-level telescopic projective framework, thereby addressing the well-known stability limitation of many explicit numerical integration methods. In the presented approach, the effective time step of the entire multilevel integration is no longer limited by the smallest time constant of the circuit so as to safeguard stability. Rather, it is controlled solely by the accuracy requirement. This makes it possible to explore the natural parallelizability of such explicit integration method for parallel circuit simulation. We demonstrate the potential of the presented approach and its parallel implementation on multi-core machines with encouraging initial results.

A parallel circuit simulator, iPRIDE, which uses a direct solution method and runs on a shared-memory multiprocessor is described. The simulator is based on a multilevel node tearing approach which produces a nested bordered-block-diagonal (BBD) form of the circuit equation matrix. The parallel solution of the nested BBD matrix is described. Its efficiency is shown to depend on how the circuit is partitioned as well as the sequence in which the concurrent tasks (scheduling) are solved. A partitioning heuristic is proposed, assuming that an arbitrary number of processors is available. Scheduling methods are studied when the number of processors is fixed. A method for determining the optimal level of partitioning, which depends on the number of processors as well as the scheduling methods, is described. The program is implemented on an ALLIANT FX/8 multiprocessor with shared memory. The performance of the program is reported. >

Hardware description language (HDL) simulation is the fundamental means of IC verification. The complexity of modern VLSI is constantly posing serious challenges to HDL simulators. We developed a parallel HDL simulation framework in which Verilog HDL is translated into a multithreaded program for parallel execution on an ×86 multi-core processor by following a conservative parallel simulation protocol. We identified two essential problems, deterministic initialization and concurrent memory simulation, which are critical to robust logic simulation. Efficient solutions based on theoretic analysis are proposed to address the problems. Experimental results prove the effectiveness of our simulation framework.

Solution of PDEs-electrically coupled systems with electrical analogy

Summary Desktop computing is undergoing a revolution with parallel processing on workstations. Parallel streamline simulators have been developed for shared memory architecture systems. In this paper, we discuss the implementation and performance analysis of a shared memory architecture commercial parallel streamline simulator based on native threading technology for both Windows® and Linux® operating systems. In general the streamline simulation algorithm is relatively straightforward to parallelize, however, there are several challenges that require special attention in order to avoid computing bottlenecks and inconsistent results. Repeatability of parallel simulation results is a well-known challenge. A data-accumulation scheduling algorithm designed to ensure repeatable results independent of the number of processing units has been implemented. The algorithm is supplemented by an efficient loadbalancing algorithm, to minimize processor idle time. Parallel scalability for various model characteristics and streamline solver options is analyzed. We have observed almost linear scalability up to 10 threads and a speed up factor of three to seven for simulation runs using a 1D explicit upwind finite difference solver to solve the transport problem along streamlines. The front tracking solver is inherently fast and does not gain significantly from parallelization. The run time of a serial simulation using the front-tracking solver is less than that of a parallel explicit solver run using up to 12 threads. The memory consumption of the front tracker is slightly higher than the explicit solver but overall streamline simulations are very memory efficient, enabling large geo-scale models to be simulated efficiently on 64-bit workstations. Complex three-phase blackoil simulation problems require a larger number of timesteps steps and speedup degrades as run time becomes dependent on the efficiency of the pressure solver. The results produced by our parallel streamline simulator are repeatable for any number of threads, and the algorithm used to achieve repeatability has little impact on performance.

Multi-agent systems are a model of distributed computing. Agents perceve their environment and a classical agent percept is a kind of odour sensing. The odour is spread in the environment by resources, and is simulated by a value which increases as the agent approaches the resource. A useful model of odour propagation is the wave propagation model. This article discusses some sequential and parallel methods to implement it. The mixing between these sequential and parallel methods is also shown, and the performance of some of them on two shared-memory parallel architectures is introduced.KeywordsExecution TimeDomain DecompositionParallel MethodSequential AlgorithmSynchronisation PointThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

This document is intended to contain a detailed description of the mathematical formulation of Xyce, a massively parallel SPICE-style circuit simulator developed at Sandia National Laboratories. The target audience of this document are people in the role of 'service provider'. An example of such a person would be a linear solver expert who is spending a small fraction of his time developing solver algorithms for Xyce. Such a person probably is not an expert in circuit simulation, and would benefit from an description of the equations solved by Xyce. In this document, modified nodal analysis (MNA) is described in detail, with a number of examples. Issues that are unique to circuit simulation, such as voltage limiting, are also described in detail.