Parallel transistor level full-chip circuit simulation

This paper discusses the development of a parallel SPICE circuit simulator using the direct method on a cloud-based heterogeneous cluster, which includes multiple HPC compute nodes with multi-sockets, multicores, and GPUs. A simple model is derived to optimally partition the circuit between the compute nodes. The parallel simulator is divided into four major kernels: Partition Device Model Evaluation (PME), Partition Matrix Factorization (PMF), Interconnection Matrix Evaluation (IME), and Interconnection Matrix Factorization (IMF). Another model is derived to assign each of the kernels to the most suitable execution platform of the Amazon EC2 heterogeneous cloud. The partitioning approach using heterogeneous resources has achieved an order-of-magnitude speedup over optimized multithreaded implementations of SPICE using state of the art KLU and NICSLU packages for matrix solution.

A parallel circuit simulator was implemented on the iPSC system. Concurrent model evaluation, hierarchical BBDF (bordered block diagonal form) reordering, and distributed multifrontal decomposition to solve the sparse matrix are used. A speedup of six times has been achieved on an eight-processor iPSC hypercube system. >

This paper considers utilizing the popular ITA (Iterated Timing Analysis) algorithm in CSM (Combining Simulation Method) to do parallel large-scale circuit simulation. An automatic partitioning method for jobs of CSM is presented, in which the related load balancing issue is also discussed. All proposed methods have been implemented and tested. Experimental results justify pleasing effects of proposed methods.

During the last years, multilevel methods have been applied in parallel circuit simulation. However, aiding the convergence of multilevel methods has gained only a little notice. This paper presents a combined Newton-Raphson and Gauss-Newton (NRGN) multilevel method for parallel circuit simulation in a networked environment. The NRGN method is formulated such that convergence aiding methods can be effectively applied. The example simulations show that, especially with step-size adjusting methods, the NRGN method improves the convergence and thus the speed of parallel circuit simulation.

This paper presents the results of an experimental study to evaluate the effectiveness of parallel simulation in reducing the execution time of gate-level models of VLSI circuits. Specific contributions of this paper include (i) the design of a gate-level parallel simulator that can be executed, without any changes on both distributed memory and shared memory parallel architectures, (ii) demonstrated speedups with both conservative and optimistic simulation protocols (almost all previous studies on circuit simulation have failed to extract speedups with conservative protocols); in particular we showed that a speedup of about 3 was obtained on 8 processors of Sparc1000 for conservative algorithms and about 2 for optimistic algorithms for circuits in the ISCAS85 benchmark suite; and (iii) performance comparison between shared memory and distributed memory implementations of the simulator.

We present a method of automatically generating circuit designs using evolutionary search and a set of circuit constructing primitives arranged in a linear sequence. This representation has the desirable property that virtually all sets of circuit-constructing primitives result in valid circuit graphs. While this representation excludes certain circuit topologies, it is capable of generating a rich set of them including many of the useful topologies seen in hand-designed circuits. Our system allows circuit size (number of devices), circuit topology, and device values to he evolved. Using a parallel genetic algorithm and circuit simulation software, we present experimental results as applied to three analog filter and two amplifier design tasks. In all tasks, our system is able to generate circuits that achieve the target specifications. Although the evolved circuits exist as software models, detailed examinations of each suggest that they are electrically well behaved and thus suitable for physical implementation. The modest computational requirements suggest that the ability to evolve complex analog circuit representations in software is becoming more approachable on a single engineering workstation.

Multi-level numerical methods that obtain the exact solution of a linear system are presented. The methods are devised by combining ideas from the full multi-grid algorithm and perfect reconstruction filters. The problem is stated as whether a direct solver is possible in a full multi-grid scheme by avoiding smoothing iterations and using different coarse grids at each step. The coarse grids must form a partition of the fine grid and thus establishes a strong connection with domain decomposition methods. An important analogy is established between the conditions for direct solution in multi-grid solvers and perfect reconstruction in filter banks. Furthermore, simple solutions of these conditions for direct multi-grid solvers are found by using mirror filters. As a result, different configurations of direct multi-grid solvers are obtained and studied.

This work exploits the recently developed telescopic projective numerical integration method for efficient parallel circuit simulation. Stable explicit numerical integration is achieved by adopting an explicit inner integrator (e.g. forward Euler) in a multi-level telescopic projective framework, thereby addressing the well-known stability limitation of many explicit numerical integration methods. In the presented approach, the effective time step of the entire multilevel integration is no longer limited by the smallest time constant of the circuit so as to safeguard stability. Rather, it is controlled solely by the accuracy requirement. This makes it possible to explore the natural parallelizability of such explicit integration method for parallel circuit simulation. We demonstrate the potential of the presented approach and its parallel implementation on multi-core machines with encouraging initial results.

This paper presents the results of an experimental study to evaluate the effectiveness of multiple synchronization protocols and partitioning algorithms in reducing the execution time of switch-level models of VLSI circuits. Specific contributions of this paper include: (i) parallelizing an existing switch-level simulator such that the model can be executed using conservative and optimistic simulation protocols with minor changes, (ii) evaluating effectiveness of several partitioning algorithms for parallel simulation, and (iii) demonstrating speedups with both conservative and optimistic simulation protocols for seven circuits, ranging in size from 3K transistors to about 87K transistors.

A Domain Decomposition (DD) method for solving time-harmonic aeroacoustic problems is presented. The computational domain is decomposed into subdomains, and the aerodynamic-aeroacoustic boundary-value problem is solved independently for each subdomain. On the artificially introduced subdomain boundaries impedance-type transmission conditions are imposed, which assure the uniqueness of the solution. The Finite Element method is used to discretize the subdomain problems. A direct solver (LU factorization) is used to solve the subdomain systems of equations and an iterative scheme updates the transmission conditions to recover the global solution. This DD method is applied to solve the classical problem of a thin airfoil in a transverse gust. The problem is formulated in terms of the unsteady pressure, and exact non-reflecting conditions are imposed on the outer computational boundary. The accuracy of the numerical scheme is validated by comparison with existing solutions for both the near-field unsteady pressure and the farfiled radiated sound. The convergence as well as the computational time and memory requirements of the present method are investigated. It is shown that by combining the subdomain direct solvers with global iterations, this DD method significantly reduces both the computational time and the memory requirements. The present algorithm is particularly suited for parallel computing.

While the emergence of multi-core shared-memory machines offers a promising computing solution to ever complex chip design problems, new parallel CAD methodologies must be developed to gain the full benefit of these increasingly parallel computing systems. We present a parallel transient simulation methodology and its multi-threaded implementation for general analog and digital ICs. Our new approach, Waveform Pipelining (abbreviated as WavePipe), exploits coarsegrained application-level parallelism by simultaneously computing circuit solutions at multiple adjacent time points in a way resembling hardware pipelining. There are two embodiments in WavePipe: backward and forward pipelining schemes. While the former creates independent computing tasks that contribute to a larger future time step by moving backwards in time, the latter performs predictive computing along the forward direction of the time axis. Unlike existing relaxation methods, WavePipe facilitates parallel circuit simulation without jeopardying convergence and accuracy. As a coarse-grained parallel approach, WavePipe not only requires low parallel programming effort, more importantly, it creates new avenues to fully utilize increasingly parallel hardware by going beyond conventional finer grained parallel device model evaluation and matrix solutions.

We investigate a domain decomposition method (DDM) of finite element method (FEM) using Intel's many integrated core (MIC) architecture in order to determine the most effective MIC usage. For this, recently introduced high-scalable parallel method of DDM is first introduced with a detailed procedure. Then, the Intel's Xeon Phi MIC architecture is presented to understand how to apply the parallel algorithm into a multicore architecture. The parallel simulation using the Xeon Phi MIC has an advantage that traditional parallel libraries such as the message passing interface (MPI) and the open multiprocessing (OpenMP) can be used without any additional libraries. We demonstrate the DDM using popular libraries for solving linear algebra such as the linear algebra package (LAPACK) or the basic linear algebra subprograms (BLAS). Moreover, both MPI and OpenMP are used for parallel resolutions of the DDM. Finally, numerical parallel efficiencies are validated by a two-dimensional numerical example.

The goal of this paper is to develop a parallel algorithm for the direct solution of large sparse linear systems and integrate it into domain decomposition methods. The computational effort for these linear systems, often encountered in numerical simulation of structural mechanics problems by finite element codes, is very significant in terms of run-time and memory requirements.In this paper, a two-level parallelism is exploited. The exploitation of the lower level of parallelism is based on the development of a parallel direct solver with a nested dissection algorithm and to introduce it into the FETI methods. This direct solver has the advantage of handling zero-energy modes in floating structures automatically and properly. The upper level of parallelism is a coarse-grain parallelism between substructures of FETI. Some numerical tests are carried out to evaluate the performance of the direct solver.

A numerical implementation of the Domain Decomposition (DD) method for parallel computation of time-harmonic waves is presented. The Finite Element method on unstructured mesh is employed to discretize the boundary-value problem. A nonover-lapping mesh partitioning is used to build an overlapping domain decomposition. The algorithm also defines the new subdomain boundaries, other than the original boundaries of the global computational domain, on which transmission conditions are introduced. The independent subdomain problems can be solved concurrently, one problem per processor, on a parallel computer. The iterative scheme used to update the subdomain transmission conditions is computationally efficient and only swaps the nodal values in the overlapping region between adjacent subdomains. For exterior problems, the communication required to update the conditions on the outer boundary is substantially reduced by employing a modified Dirichlet-to-Neumann (DtN) map with truncated support. Numerical results are presented for a radiation model problem. It is shown that the DtN nonreflecting conditions eliminate spurious reflections and that the iterative scheme leads to a continuous global solution. The DD algorithm also has a very good convergence rate and significantly reduces memory requirement in comparison with a direct solver.

The efficient analysis of power grids is a crucial yet computationally challenging task in integrated circuit (IC) design, given the shrinking power supply voltage of ultra deep-submicron VLSI design. Different from the conventional modified nodal analysis technique, this paper introduces MAUnet, an innovative machine-learning model that redefines state-of-the-art full-chip static IR drop prediction. MAUnet ingeniously integrates multi-scale convolutional blocks, attention mechanisms, and U-Net architecture to optimize prediction accuracy. The multi-scale convolutional blocks significantly enhance feature extraction from image-based data, while the attention mechanism precisely identifies hotspot regions. The U-Net architecture, on the other hand, enables scalable image-to-image prediction applicable to circuits of any size. Uniquely, MAUnet also incorporates a pioneering fusion method that synergies both power grids and image-based data. Additionally, we introduce a low-rank approximation transfer learning technique to extend MAUnet's applicability to unseen test cases. Benchmark tests validate MAUnet's superior performance, achieving an average error of less than 6% relative to the average IR drop on three benchmarks. The performance enhancements offered by our proposed method are substantial, outperforming the current state-of-the-art method, IREDGe, by considerable margins of 29%, 65%, and 68% in three canonical benchmarks. Transfer learning is validated to enable model to achieve effective improvement on real circuit test cases. Compared to commercial tools, which often require hours to deliver results, the proposed method provides orders of magnitude speed-up with negligible error in practice.