WavePipe

With a relatively small number of components, analog ICs are much more vulnerable to piracy, and especially reverse engineering, than many digital ICs. However, analog IC security has received much less research attention than digital ICs. We introduce a combinational locking technique using configurable current mirror for analog IC protection. The locking circuit is designed by applying Satisfiability Modulo Theories. With the locking system, only a single key value can make analog IC operate properly while the other key values result in significant performance degradation or malfunction. Moreover, circuit output is not monotone function with respect to key values and thus systematic attack is difficult to be effective. Experimental results demonstrate that this technique can largely thwart analog IC piracy with limited overhead.

Developing fuzzy applications contain many steps. Each part may require lots of computation cycles depending on applications and target platforms. In this work, we study the parallelism in fuzzy systems using openMP and its possibility in embedded plaforms. Two versions of the parallelization are mentioned: fine-grained and coarse-grained parallelism. In our study, we found that the coarse-grained approach is more effective due to the overhead of openMP which becomes more visible in the low-speed CPU. Thus, the coarse-grained approach is suggested. Two versions using paralle-for and section are proposed. Two versions give different speedup rate depending on characteristics of the applications and fuzzy parameters. In general, the experiments convey that as the system runs continuously the openMP implementation can achieve a certain speedup, overcoming the openMP overhead by the proposed parallelization schemes.

A dynamic synchronization method to realize soft defect localization applied on digital and mixed-mode analog ICs in failure analysis

High-speed ICs for 20-40-Gbit/s time-division multiplexing (TDM) optical transmission systems have been designed and fabricated by using InP/InGaAs heterojunction-bipolar-transistor (HBT) technology. This paper describes four analog ICs and four digital ICs: a five-section cascode distributed amplifier with a gain of 9.5 dB and a bandwidth of 50 GHz, a three-section single-end-to-differential converter with a bandwidth of 40 GHz, a cascode differential amplifier with a gain of 10.5 dB and a bandwidth of 64 GHz, a preamplifier with a gain of 41.9 dB/spl Omega/ and a bandwidth of 39 GHz, a modulator driver with an output voltage swing of 3.2 V peak-to-peak and rise and fall times of 16 and 15 ps, a 40-Gbit/s selector, a 20-Gbit/s D-type flip-flop, and a static frequency divider with an operating range of 2.0-44.0 GHz. All the ICs were measured with on-wafer RF probes.

This paper discusses the development of a parallel SPICE circuit simulator using the direct method on a cloud-based heterogeneous cluster, which includes multiple HPC compute nodes with multi-sockets, multicores, and GPUs. A simple model is derived to optimally partition the circuit between the compute nodes. The parallel simulator is divided into four major kernels: Partition Device Model Evaluation (PME), Partition Matrix Factorization (PMF), Interconnection Matrix Evaluation (IME), and Interconnection Matrix Factorization (IMF). Another model is derived to assign each of the kernels to the most suitable execution platform of the Amazon EC2 heterogeneous cloud. The partitioning approach using heterogeneous resources has achieved an order-of-magnitude speedup over optimized multithreaded implementations of SPICE using state of the art KLU and NICSLU packages for matrix solution.

This work exploits the recently developed telescopic projective numerical integration method for efficient parallel circuit simulation. Stable explicit numerical integration is achieved by adopting an explicit inner integrator (e.g. forward Euler) in a multi-level telescopic projective framework, thereby addressing the well-known stability limitation of many explicit numerical integration methods. In the presented approach, the effective time step of the entire multilevel integration is no longer limited by the smallest time constant of the circuit so as to safeguard stability. Rather, it is controlled solely by the accuracy requirement. This makes it possible to explore the natural parallelizability of such explicit integration method for parallel circuit simulation. We demonstrate the potential of the presented approach and its parallel implementation on multi-core machines with encouraging initial results.

The paper proposes an initial benchmark set, suitable for substrate analysis and test. The aim is to help accurately represent electrical noise injected into and picked up from substrate in a variety of high performance circuits. Creating an accurate image of such noise is becoming a critical requirement with the expansion of real plug-and-play style designs. Several important methods for the analysis of substrate parasitic coupling are reviewed in light of the effect substrate noise has on the performance of analog and digital ICs over a wide frequency spectrum. The requirements and formats for each benchmark are described in full detail to allow possible algorithmic as well as signal integrity tests.

The development of CAD tools for Integrated Circuit engineers designing digitial circuits is much more advanced than that of tools for analog circuit design. This paper discusses specific analog needs in modeling and simulation, layout and verification, and test development. The advent of mixed analog and digital ICs, sometimes combining bipolar and MOS processes on the same chip increases the need for CAD improvements. The need for better MOS models is stressed, including the need for mismatch and temperature differential analyses. Simulators with better analog functionality, layout tools which recognize thermal and stray coupling effects, and better test programming tools are also needed.

The application of parallel computers to reservoir simulation is studied with the aid of two recently introduced Multiple Instruction, Multiple Data (MIMD) computers. The problems posed by reservoir simulators are shown to be particularly well suited for such parallel computers* Fundamental parallel programming techniques using Fortran are presented for the Hetrogeneous Element Processor (HEP) produced by Denelcor and the iPSC Hypercube produced by Intel. These techniques are then applied to two of the most time consuming tasks in reservoir simulation: forming the matrix coefficients and producing a sparse matrix solution. The problem of parallel formation of sparse matrix coefficients is addressed for the single and multiphase cases using both black oil and compositional fluid models. Parallel sparse matrix solution is addressed by considering D4 ordered Gaussian elimination, and the multigrid, conjugate gradient, and Successive Over-Relaxation (SOR) methods. Three parallel algorithms based on SOR are developed to illustrate the possible diversity of parallel algorithms. The red-black and multicolored SOR methods which are often used on vector machines are shown to be easily adaptable to parallel MIMD machine. Matrix partitioning and a new method of iteration pipelining are also presented as parallel SOR methods. The various SOR algorithms, in parallel form, are mapped onto the HEP to illustrate the speedups currently possible on an MIMD machine. Projections are made on the future importance of these types of machines to reservoir simulation.

The cloud-assisted intelligent systems have attracted extensive attention due to their powerful data analysis and computation capabilities. However, how to handle encrypted data remains a challenging problem in intelligent systems. A promising solution is searchable symmetric encryption (SSE), which enables a client to privately outsource their data to the cloud while preserving keyword search functionality. In practice, dynamic SSE is more practical and supports efficient data addition and deletion. Unfortunately, data update will leak some additional information which can be exploited to break data privacy. To address this issue, forward and backward secure SSE schemes are proposed to reduce the leakage of data update. That is, forward security guarantees that the newly updated documents cannot reveal the previously searched keywords, while backward security guarantees that the server cannot recover the deleted documents. However, the existing forward and backward secure SSE schemes mainly consider curious-but-honest server. How to verify the soundness and completeness of search results is still a challenge. In this paper, we propose a noninteractive verifiable dynamic SSE scheme with forward and backward security from two universal accumulators. Specifically, the server in our scheme only needs one roundtrip to return the nondeleted search results to the client, which saves the communication overhead dramatically. Besides, our scheme can achieve public verification that anyone can verify the search results but not only the client who has the private key. Finally, we give a formal security analysis and compare the proposed scheme with other related work, the results show that our scheme can achieve the desired security properties with practical efficiency.

In this paper, we present a fully parallel transistor level full-chip circuit simulation tool with SPICE-accuracy for general circuit designs. The proposed overlapping domain decomposition approach partitions the circuit into a linear subdomain and multiple non-linear subdomains based on circuit non-linearity and connectivity. Parallel iterative matrix solver is used to solve the linear domain while non-linear subdomains are parallelly distributed into different processors topologically and solved by direct solver. To achieve maximum parallelism, device model evaluation is done parallelly. Parallel domain decomposition technique is used to iteratively solve the different partitions of the circuit and ensure convergence. Orders of magnitude speedup over SPICE is observed for sets of large-scale circuit designs on up to 64 processors.

VeSTIC technology [1, 2] is a very promising concept of digital, analog and mixed mode ICs design, providing very large scale of integration, extreme layout regularity, as well as the possibility of manufacturing cost reduction and of fully three-dimensional integration. These features seem to be very attractive also in the case of MEMS systems, in particular MAP sensors. With regard to prospective applications, a first insight to noise spectra and radiation hardness of the field-effect VeSTIC devices has been performed and confirms their usefulness.

The purpose of this paper is to present a methodology for circuit and realistic fault extraction, and its implementation in a new tool, lobs, to be included in a virtual test environment, DOTLab. Digital, analog and mixed signal ICs, implemented in CMOS, bipolar or BiCMOS technologies are handled both in Manhattan and 45/spl deg/ geometries. Higher level design data, obtained in the top-down design flow, is used for realistic fault characterization. A sliding window algorithm is extended for fault extraction of non-orthogonal geometries. An accurate critical area evaluation algorithm is proposed to compute the probability of occurrence of the defects. Over 100,000 transistor ICs are analyzed for bridging defects.

We propose a system that can be used to generate a dark soliton pulse array by using multidark soliton sources in the microring resonators and an optical multiplexer, where the different dark soliton center wavelengths can be generated. To verify the simulation results, the experimental setup was employed by using the Brillouin enhanced fiber laser in the fiber ring resonator (loop) system, where two different systems, called forward and backward schemes, were used to generate the dark soliton arrays. Three different center wavelengths of dark solitons were generated and seen to be in good agreement with the theoretical results.

We study an identification problem which estimates the parameters of the underlying random distribution for uncertain scalar conservation laws. The hyperbolic equations are discretized with the so-called discontinuous stochastic Galerkin method, i.e., using a spatial discontinuous Galerkin scheme and a Multielement stochastic Galerkin ansatz in the random space. We assume an uncertain flux or uncertain initial conditions and that a data set of an observed solution is given. The uncertainty is assumed to be uniformly distributed on an unknown interval and we focus on identifying the correct endpoints of this interval. The first-order optimality conditions from the discontinuous stochastic Galerkin discretization are computed on the time-continuous level. Then, we solve the resulting semi-discrete forward and backward schemes with the Runge Kutta method. To illustrate the feasibility of the approach, we apply the method to a stochastic advection and a stochastic equation of Burgers' type. The results show that the method is able to identify the distribution parameters of the random variable in the uncertain differential equation even if discontinuities are present.