Xyce parallel electronic simulator design : mathematical formulation, version 2.0.

This paper discusses the development of a parallel SPICE circuit simulator using the direct method on a cloud-based heterogeneous cluster, which includes multiple HPC compute nodes with multi-sockets, multicores, and GPUs. A simple model is derived to optimally partition the circuit between the compute nodes. The parallel simulator is divided into four major kernels: Partition Device Model Evaluation (PME), Partition Matrix Factorization (PMF), Interconnection Matrix Evaluation (IME), and Interconnection Matrix Factorization (IMF). Another model is derived to assign each of the kernels to the most suitable execution platform of the Amazon EC2 heterogeneous cloud. The partitioning approach using heterogeneous resources has achieved an order-of-magnitude speedup over optimized multithreaded implementations of SPICE using state of the art KLU and NICSLU packages for matrix solution.

A parallel circuit simulator, iPRIDE, which uses a direct solution method and runs on a shared-memory multiprocessor is described. The simulator is based on a multilevel node tearing approach which produces a nested bordered-block-diagonal (BBD) form of the circuit equation matrix. The parallel solution of the nested BBD matrix is described. Its efficiency is shown to depend on how the circuit is partitioned as well as the sequence in which the concurrent tasks (scheduling) are solved. A partitioning heuristic is proposed, assuming that an arbitrary number of processors is available. Scheduling methods are studied when the number of processors is fixed. A method for determining the optimal level of partitioning, which depends on the number of processors as well as the scheduling methods, is described. The program is implemented on an ALLIANT FX/8 multiprocessor with shared memory. The performance of the program is reported. >

Modified nodal analysis (MNA) can be considered as the most adopted method in circuit simulation programs. Once node equations were written and complemented with those from the current controlled branches, a nonlinear system of algebraic and/or differential equations is obtained. In general, by using linear multistep integration methods, differential equations are recast as nonlinear algebraic ones, which are solved through the Newton method at each integration time step. While computer precision is not an issue in most situations, some specific but frequent cases yield ill-conditioned or singular matrices even in originally well posed circuits. This drawback can occur in different situations namely in presence of strongly nonlinear elements and/or when very small integration time steps are used. In the second case, very large conductances in the companion model of capacitors can introduce roundoff errors. In this paper, a transformation of the MNA that overcomes these problems is proposed. It is based on a suitable recombination of equations and electrical variables of the conventional MNA and it can be easily implemented in a circuit simulator.

A parallel circuit simulator was implemented on the iPSC system. Concurrent model evaluation, hierarchical BBDF (bordered block diagonal form) reordering, and distributed multifrontal decomposition to solve the sparse matrix are used. A speedup of six times has been achieved on an eight-processor iPSC hypercube system. >

A description is given of a simple but effective modification to a well-known circuit formulation method, modified nodal analysis (MNA), to reduce the number of equations while formulating the circuit equations. For this purpose, a set of simple rules are presented. This new method is compared with the original MNA for simplicity and memory space. The new method is found to be superior to MNA in memory requirement and run time. The complete method of implementing the rules with examples of its use is presented. >

This paper presents a simulation technique and a computer program for fast DC analysis of MOS transistor based VLSI circuits. Time domain analysis of a VLSI circuit is evaluated by a piecewise constant waveform approximation. This approximation is realized by repeatedly applying the developed DC analysis engine with initial conditions. All proposed methods such as device modeling, circuit partitioning and event-driven simulation were implemented and combined with such well known algorithms as modified nodal analysis (MNA), Katzenelson algorithm and Gaussian elimination in the form of a circuit simulation program: SAMOC. Time domain waveforms and benchmark circuit simulation results comparison of SPICE and SAMOC are presented.

This paper investigates the index of differential‐algebraic equations (DAEs) that arise in modeling of electric circuits with gyrators. A gyrator is a two‐port network element whose constitutive equations are defined by a skew‐symmetric matrix. While the index analysis of DAEs in circuit simulation has been extensively studied, the existing characterizations are not applicable to circuits that include gyrators. For linear time‐invariant circuits with gyrators, we analyze the index of DAEs using a matroid‐theoretic approach. We show that the problem of determining whether DAEs arising from the hybrid analysis have index at most one or not is reduced to a linear matroid parity problem. We also provide a structural characterization for DAEs arising from the modified nodal analysis (MNA), and extend it to nonlinear circuits, generalizing a structural characterization that is well known in the index analysis of the MNA models.

This paper presents the results of an experimental study to evaluate the effectiveness of parallel simulation in reducing the execution time of gate-level models of VLSI circuits. Specific contributions of this paper include (i) the design of a gate-level parallel simulator that can be executed, without any changes on both distributed memory and shared memory parallel architectures, (ii) demonstrated speedups with both conservative and optimistic simulation protocols (almost all previous studies on circuit simulation have failed to extract speedups with conservative protocols); in particular we showed that a speedup of about 3 was obtained on 8 processors of Sparc1000 for conservative algorithms and about 2 for optimistic algorithms for circuits in the ISCAS85 benchmark suite; and (iii) performance comparison between shared memory and distributed memory implementations of the simulator.

A charge oriented mixed multirate method for a special class of index-1 network equations in chip design

Memristor is a two-terminal non-linear passive electrical device. After its recently successful fabrication, a variety of applications based on memristor have been explored, such as non-volatile memory, reconfigurable computing and neural network. However, one major challenge when designing hybrid CMOS memristor integrated circuit is the lack of SPICE-like simulator for design validation. Current approach is to describe memristor device with equivalent circuit, which is however extremely time-consuming for large scale design simulation due to additional modeling components. In this paper, a memristor SPICE simulator is introduced based on the recent new modified nodal analysis (MNA) framework, which can effectively support the non-conventional state variable such as doping ratio of memristor. As such, the memristor device can be stamped into state matrix similarly as one BSIM MOSFET. Compared with equivalent circuit simulation approach, our new MNA based approach exhibits 40x less simulation time for a 32×32 memristor crossbar circuit. A hybrid CMOS memristor circuit for classic conditioning training has also been studied by the developed SPICE simulator.

The use of pathological elements (i.e., nullators, norators, and the voltage mirror-current mirror pair) as universal active elements opens up the possibility to model the behavior of active devices with either differential features or input-output multiples, in order to be used in analysis tasks of linear(ized) analog circuits. This brief tries on the modeling this class of active devices, which is carried out by considering the impedance characteristics along with the behavior equation of each active device, the kind of signal to be processed and by applying the pathological element properties. In order to obtain a more realistic model, not only parasitic elements associated to the input-output terminals of each active device are considered, but the tracking errors of voltage and current differential followers modeled with grounded pathological elements and admittances are also included. Due to that the gain and tracking errors are finites and of limited bandwidth, a two-pole model is used for each of them in order to include their contributions on the symbolic expressions computed. Because the behavior of fully-differential amplifiers is modeled with grounded pathological elements, a standard nodal analysis can be performed. This imply that not only the size of the admittance matrix is smaller than those generated by applying modified nodal analysis (MNA) method, for instance, but also the number of nonzero elements and the generation of cancellation-terms are both reduced. As a result, the computational complexity during the solution of the system of equations is reduced when recursive determinant-expansion techniques are applied. Examples are described and compared with the MNA method, in order to show the usefulness of the proposed models to compute fully-symbolic small-signal characteristics of analog circuits containing fully-differential active devices and/or with input-output multiples.

A dye-sensitized solar cell model implementable in electrical circuit simulators

In this study, the analysis of fixed capacitor thyristor controlled reactor (FC-TCR), one of Static VAR compensation techniques, is performed by modified nodal analysis (MNA). In the analysis, semiconductor elements are modelled with two- valued resistor concept. The resulting equations are solved by Trapezoidal method, used in numerical analysis. All of the simulation results are obtained in Matlab M-File environment.

This paper presents a hybrid approach to the investigation of the performance of printed circuit boards (PCB) by examining the impact of parasitic parameters of the board design on the efficiency of a device. First, parasitic parameters are extracted from the board layout by 3D quasistatic field solvers. Second, the corresponding equivalent circuit is constructed. Third, the extracted parasitic circuits are incorporated into functional circuit model. Finally, Modified Nodal Analysis (MNA) is used to examine a complete network. The hybridization makes it possible to vary circuit parameters and layout independently to achieve maximum system performance. Validation of the proposed method is performed by comparison of simulation results with measurements of GSM band signal amplifier.

This paper presents a hybrid approach to the frequency and time domain simulation of complex cable systems with arbitrary linear or linearized circuits at terminations. Depending on the type of cables to be investigated, either FDTD/MNA or MTL/MNA approach can be recommended. In FDTD/MNA scheme 1D-FDTD method is applied to solve the transient response of a cable system, which is then used together with circuits of termination devices to simulate the complete network by modified nodal analysis (MNA). In the second scheme, MTL theory is used to extract equivalent circuit models of cables. All extracted equivalent circuits are then merged with termination devices and solved using specialized MNA-based circuit solver. Both methods are speed-oriented, provide accurate results and can be used for fast simulation of large-scale cable systems. Validation of the proposed methods is performed by comparison with measurements of high voltage shielded cable test setup. Two application examples demonstrate the potential of the proposed approaches for simulation of large-scale cable systems - automotive harness and office wiring network.