Parameterized AES-Based Crypto Processor for FPGAs

In this paper, a method for image encryption is proposed based on a novel approach using chaos and transcendental numbers for generating the substitution box and the ciphering keys. The Chaotic Pi Ciphering (CPC) is a robust symmetric cryptosystem of the substitution-permutation-network type, that ciphers images in ten rounds. The objective of CPC is to avoid some general weakness points in cryptosystems, such as the vulnerability to certain types of attacks or the encryption with data loss. The number of rounds can be increased up to 14, with an even further increment of the ciphering security. An 8×8 substitution box is constructed using chaos, and its value of the Differential Power Analysis is lower than the corresponding to the Advanced Encryption Standard (AES). It makes CPC more resistant to differential and linear attacks than AES. CPC has approximately 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">512</sup> keys, presenting a high resistance to brute-force attacks. Chaos is produced by a nonlinear differential equation, and the Walsh function is applied to measure the nonlinearity of the box. The transcendental number pi and a positive integer are employed to generate the schedule keys, and the key length is equal to the image size. The randomness of the encrypted images is evaluated with four tests: entropy, correlation, Discrete Fourier Transform, and a goodness-of-fit test using the chi square distribution χ <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . CPC was tested using well-known images from the related literature, and its performance was compared to the corresponding to AES. The results show a good entropy and a high randomness, indicating a high-quality ciphering.

This paper presents the design and implementation of low power 32-bit encrypted and decrypted MIPS processor for Data Encryption Standard (DES), Triple DES, Advanced Encryption Standard (AES) based on MIPS pipeline architecture. The organization of pipeline stages has been done in such a way that pipeline can be clocked at high frequency. Encryption and Decryption blocks of three standard cryptography algorithms on MIPS processor and dependency among themselves are explained in detail with the help of a block diagram. Clock gating technique is used to reduce the power consumption in MIPS crypto processor. This approach results in processor that meets power consumption and performance specification for security applications. Proposed Implementation approach concludes higher system performance while reducing operating power consumption. Testing results shows that the MIPS crypto processor operates successfully at a working frequency of 218MHz and a bandwidth of 664Mbits/s.

&lt;p&gt;The paper describes the Low power 32-bit encrypted MIPS processor based on AES algorithm and MIPS pipeline architecture. The pipeline stages of MIPS processor are arranged in such a way that pipeline can be clocked at high frequency and clock gating technique is used for reducing power consumption. Encryption blocks of Advanced Encryption Standard (AES) cryptosystem and dependency among pipeline stages are explained in detail with the help of block diagram. In order to reduce the power consumption, especially for portable devices and security application switching activity is used inside pipeline stages. The design has been synthesized at 40nm process technology targeting using Xilinx Virtex-6 device. The encrypted MIPS pipeline processor can work at 210MHz and power consumption is 1.313W.&lt;/p&gt;

This study compares the performance of video file encryption using the symmetric Advanced Encryption Standard (AES) and a hybrid scheme combining AES with Rivest–Shamir–Adleman (RSA). The research aims to evaluate efficiency and security trade-offs between the two approaches. Experimental tests were conducted on video files of different sizes, measuring encryption time, decryption time, and file size overhead. Results show that AES achieves faster processing, with average encryption time of 0.0773 seconds and decryption time of 0.1097 seconds. In contrast, the hybrid AES–RSA scheme is slower, with encryption time of 0.0854 seconds (10.4% slower) and decryption time of 0.1405 seconds (28.1% slower), due to additional RSA key operations. While AES is more efficient for real-time applications, the hybrid method provides stronger key distribution security These findings highlight the importance of selecting encryption methods based on application requirements.

A multi-algorithm Crypto-Co-Processor called Celator is presented. Celator architecture is based on a 4times4 Processing Elements systolic array, a Sequencer with a Finite State Machine (FSM) and a local memory, the Celator RAM (CRAM). Data are encrypted or decrypted by the PE array. The whole system architecture around Celator includes a Central Processing Unit (CPU) and an Interface unit between the CPU and Celator. The Sequencer controls the PE array and manages all the data transfers between the PE array and the CPU. Three multiplexers per PE allow the reconfigurability of the data path. The FSM instructions are stored in the CRAM and can be changed by the CPU: therefore the FSM is also reconfigurable. This paper focuses on the implementation of the Advanced Encryption Standard (AES) transformations on Celator. Celator can perform an AES encryption in 580 clock cycles in Electronic Codebook mode, which is less than with a general purpose processor. Finally we report performance comparisons among Celator, ARM 7 TDMI, ARM 9 and AVR microprocessors, as well as with some AES dedicated and dynamically reconfigurable circuits.

All information in data exchange transactions on communication networks travels through the network infrastructure. The network infrastructure sends various types of data, including text, images, and documents with various extensions. These documents may be private and confidential. Therefore, it is crucial to have a message security option that is not only user-friendly but also has a high level of security system complexity. The purpose of this research is to build a text message security system using the Advanced Encryption Standard (AES) algorithm on mobile devices. We can utilize it as a security solution to safeguard text messages received through mobile devices. The AES security algorithm is known to have reliability in processing data encryption and decryption. The research will describe components such as the design, implementation, and analysis of application requirements. Important features include encryption, decryption, and key management in addition to an easy-to-use UI. The research findings show that this program successfully secures text messages while maintaining the confidentiality and integrity of the data sent. Additionally, we adjusted the application's parameters to align with mobile device standards, ensuring consistent encryption and decryption procedures that users can easily operate. For application testing, we use the black box testing method to ensure that the design and application function as intended, adhere to security regulations, and provide a positive user experience. This study's results suggest that AES-based mobile messaging security applications can serve as a tool to fulfill the secure communication expectations of mobile users.

The Internet of Things makes it possible to exchange information between people, things and things, people and things, and makes information security more and more important. However, there are few standards in the field of information security of the Internet of Things. Therefore, based on the characteristics and application requirements of the Internet of Things environment, this paper optimizes the Advanced Encryption Standard (AES) and builds the data encryption standard DESI(Data Encryption Standard in IoT) in the Internet of Things environment.. The analysis shows that DESI has better security and is therefore suitable for encrypting data in the IoT environment. Keywords: Internet of Things, encryption standard, AES, DESI, information security.

The Internet of Things is a network of billions of interconnected devices that communicate over the internet. These massive devices exchange massive amounts of data every second, and that data may be sensitive and must be protected from attackers. A cryptographic solution could be used to address these issues. Conventional cryptography is unsuitable for IoT devices with limited resources; lightweight cryptography is an alternative solution. Many researchers have presented new designs and modified the existing algorithms to become lightweight versions. This paper presents a recent comparison among numerous modifications of the very popular block cipher AES-128 algorithm that have been published between 2016 and 2021 in the light-weight symmetric block cipher cryptographic field based on security, throughput, and encryption time with various message lengths. The results of the comparison indicate that the modifications, which included modifying the ShiftRow operation, modifying the MixColumn operation and combining it with the AddRoundKey operation to perform in a single cycle, and reducing the number of rounds to 6, were faster in implementation and had greater security than other studies cited.

In today's digital age, vulnerabilities in digital platforms have become a major concern, as cyber-attacks can lead to significant financial losses and privacy breaches. Encryption and authentication algorithms, such as AES and HMAC, are commonly used to secure digital platforms. However, running these algorithms in software can burden the CPU, leading to inefficiencies and potential security vulnerabilities. In this proposed paper, the implementation of a crypto-processor based on AES and HMAC to address the inefficiencies of software-based encryption and authentication. Our implementation uses AES for encryption and HMAC for integrity and authentication. By implementing these functions in hardware, we achieve greater efficiency and security, while reducing resource consumption and power usage. Our proposed crypto-processor design provides an efficient and secure solution for digital platform security, improving the overall performance of cryptographic operations. We demonstrate the effectiveness of our design through a comparison with software-based implementations of AES and HMAC, showing that our design provides a significant improvement in terms of throughput, latency, and power consumption. Our research contributes to the ongoing efforts to improve the security and efficiency of digital platforms, helping to protect sensitive data and ensure the privacy of users. Our proposed crypto-processor design provides a cost-effective and scalable solution for securing digital platforms, making it suitable for a wide range of applications in both commercial and government sectors.

The main objective of this study was to investigate the influence of using magnetized water on the mechanical properties and durability behavior in terms of freeze-thaw resistance of recycled aggregate concrete. In addition to the effect of different numbers of water rounds in the magnetic field, other variables including steel fibers, super-plasticizers and silica-fume were considered in the concrete production in order to achieve the ideal possible performance for recycled aggregate concrete made with 100% coarse aggregates replacements. For this purpose, a total of 11 concrete mixes were prepared and tested. At the first step, the effects of the mentioned variables on the basic properties, including workability, water absorption, compressive strength, splitting tensile strength, flexural strength and freeze-thaw durability test were investigated. Additionally, flexural toughness was evaluated in accordance with the post-crack strength (PCS) method and the microstructure of concrete specimens was also observed by using scanning electron microscope (SEM). The results of most experiments indicated that magnetized water, although highly effective on the mechanical properties of concrete, should not be solely utilized as a compensating factor for the defects caused by recycled coarse aggregates. The optimum toughness and durability results regarding the fiber-reinforced concrete mixes produced with recycled coarse aggregates, were related to samples containing silica-fume and 10-rounds magnetized water. Furthermore, the existence of cement replaced by 10% of silica-fume and 10-rounds magnetized water in the concrete mix MW-SF2, increased the durability of the recycled aggregate concrete by an average of approximately 63%.

These years, wireless sensor network (WSN) has emerged as an especially hot topic, which is the result of rapid advances in miniaturization, low-power circuit design, more energy-efficient wireless communication, improved small-scale energy supplies and reduced manufacturing costs. A WSN node consists of four basic components: sensing, data processing, communicating and power supply. Among these, low power technology is the spirit of WSN hardware and software design. In this paper, a novel WSN-oriented low-power processor (WO-LPP) design scheme is presented. Our processor has an 8-bit simple 3-stage pipeline event-driven RISC ISA core and 4k SRAM, 64K on-chip program flash connected by Harvard bus. At the same time, on-chip event-based task management, on-chip hardware management and power management scheme are coordinately designed with some general peripheral devices, such as time counter, real time counter, ADC, SPI, I/sup 2/C and UART interface to meet most application requirements of wireless sensor networks. An AES (advanced encryption standard) engine is also designed to address the security issue of wireless communication. Implement results show the processor is specially optimized for wireless sensor networks.

Securing the wireless Internet of Things (IoT) is a challenging issue do to their technological constraints: limited computing power, restricted batteries or inconsistent energy supply. With more than 26 billion devices connected in 2019, the expected 75 billion things by 2025 will require an even higher energy supply. Meanwhile, as smarts cities, industry and healthcare represent more than 75% of the IoT market share, these devices must be secured while limiting the impact on energy consumption. The lifetime of specific devices such as Wearable or Implantable Medical Devices (WMDs, IMDs) can then be significantly impacted. In this paper, we propose a generic design that dynamically reduces the energy consumption required by the addition of security within the IoT networks, according to the local level of battery use. This self-monitored, fully-automated, low-cost and remotely configurable mechanism adjusts the number of encryption rounds of the cryptographic primitive while guaranteeing the minimum level of security required. This method has been integrated into the Constrained Application Protocol (CoAP) with the Datagram Transport Layer Security (DTLS) using the AES-128 encryption standard, with 10 rounds (full) to 7, and can be implemented on other protocol stacks. We show a reduction in CPU power consumption of a Raspberry Pi of 19.67%. Finally, we estimate its efficiency by simulating the discharge of multiple batteries with different capacities. Our mechanism increases operating time up to 33 minutes and 15 seconds for a 10,000mAh Raspberry Pi battery when 150 messages of 4Kb per second are exchanged with an operator.

In this paper an AES crypto coprocessor that is fabricated using a 0.18-μm CMOS technology is presented. This crypto coprocessor performs the AES-128 encryption in both feedback and non-feedback modes of operation. A maximum throughput of 3.84 Gbits/s is achieved at a 330 MHz clock frequency for ECB, OFB, and CBC modes of operation. This crypto coprocessor can be programmed using the memory-mapped interface of an embedded CPU core and is tested using a LEON 32-bit (SPARC V8) processor in the ThumbPod secure system-on-chip.

The quantity of computer applications is increasing dramatically as the computer industry prospers. Meanwhile, even for one application, it has different requirements of performance and power in different scenarios. Although various processors with different architectures emerge to fit for the various applications in different scenarios, it is impossible to design a dedicated processor to meet all the requirements. Furthermore, dealing with uncertain processors significantly aggravates the burden of programmers and system integrators to achieve specific performance/power. In this paper, we propose elastic architecture (EA) to provide a uniform computing platform with high elasticity, i.e., the ratio of worst-case to best-case performance/power/performance-power trade-off, which can meet different requirements for different applications. It is achieved by dynamically adjusting architecture parameters (instruction set, branch predictor, data path, memory hierarchy, concurrency, status & control, and so on) on demand. The elasticity of our prototype implementation of EA, as Sim-EA, ranges from 3.31 to 14.34, with 5.41 in arithmetic average, for SPEC CPU2000 benchmark suites, which provides great flexibility to fulfill the different performance and power requirements in different scenarios. Moreover, Sim-EA can reduce the EDP (energy-delay product) for 31.14 % in arithmetic average compared with a baseline fixed architecture. Besides, some subsequent experiments indicate a negative correlation between application intervals’ lengths and their elasticities.

Secure multiparty computation provides specially designed cryptographic protocols for collaborative applications with private inputs and outputs. Computing with private data has been successfully demonstrated for some real-life applications. However, meeting the application requirements still requires major improvements of the protocols' performance and functionality. In this paper, we present improved building blocks and protocols for secure fixed-point arithmetic based on the framework introduced in [1], [2]. We show that the number of interaction rounds can be substantially reduced with respect to the initial solutions (e.g., multiplication in 1 round, instead of 2 rounds, division in 14 rounds, instead of 43 rounds). The new building blocks used in these protocols are of independent interest, e.g., they can provide much needed improvements for secure floating-point arithmetic.