Partial TMR in FPGAs Using Approximate Logic Circuits

This paper describes a scalable, technology-independent algorithm for the synthesis of approximate logic circuits. A low overhead, non-intrusive solution for concurrent error detection (CED) based on such circuits is described in this paper. CED based on approximate logic circuits does not impose any performance penalty on the original design. The proposed synthesis algorithm for approximate logic circuits scales with circuit size, and provides fine-grained trade-offs between area-power overhead and CED coverage.

All-Programmable System-on-Chips (APSoCs) constitute a compelling option for employing applications in radiation environments thanks to their high-performance computing and power efficiency merits. Despite these advantages, APSoCs are sensitive to radiation like any other electronic device. Processors embedded in APSoCs, therefore, have to be adequately hardened against ionizing-radiation to make them a viable choice of design for harsh environments. This paper proposes a novel lockstep-based approach to harden the dual-core ARM Cortex-A9 processor in the Xilinx Zynq-7000 APSoC against radiation-induced soft errors by coupling it with a MicroBlaze TMR subsystem in the programmable logic (PL) layer of the Zynq. The proposed technique uses the concepts of checkpointing along with roll-back and roll-forward mechanisms at the software level, i.e. software redundancy, as well as processor replication and checker circuits at the hardware level (i.e. hardware redundancy). Results of fault injection experiments show that the proposed approach achieves high levels of protection against soft errors by mitigating around 98% of bit-flips injected into the register files of both ARM cores while keeping timing performance overhead as low as 25% if block and application sizes are adjusted appropriately. Furthermore, the incorporation of the roll-forward recovery operation in addition to the roll-back operation improves the Mean Workload between Failures (MWBF) of the system by up to ≈19% depending on the nature of the running application, since the application can proceed faster, in a scenario where a fault occurs, when treated with the roll-forward operation rather than roll-back operation. Thus, relatively more data can be processed before the next error occurs in the system.

We present an error detection technique for a floating point adder which uses a checker adder of reduced precision to determine if the result is correct within some error bound. Our analysis establishes a relationship between the width of the checker adder's mantissa and the worst-case magnitude of an undetected error in the primary adder's result. This relationship allows for a tradeoff between error detection capability and area overhead that is not offered by any previously developed floating point adder checking schemes. Experimental results of fault injection experiments are presented which support our analysis.

The paper presents the results of fault injection experiments to analyse the error syndrome of a microcomputer system. The faults have been injected at chip level in VHDL models, using an injection tool designed with this purpose. We have carried out a set of injection experiments. Transient faults has been injected (stuck-at and open line) on both the signals and variables of both processor and memory. We have classified and analysed the pathology of the errors and measured their latency. The results have shown that the majority of errors produced in the signals are of type Control Flow (46%), with a propagation latency of around half clock cycle. On the other hand, the prevailing errors in the model variables are of type Data (65%), with a propagation latency of about 2.5 clock cycles. These results can be used to focus the design of fault detection and fault tolerance mechanisms to increase the system dependability.

Object-based distributed systems are becoming increasingly popular since objects provide a secure and easy means of using the abstraction of shared memory. In this paper we develop a new object-based control flow checking technique called (COTM) to detect errors due to hardware faults in such systems. The proposed technique monitors objects and thread flow across objects in two stages. The first stage applies control flow checking for every object invocation. In the second stage, the legality of a terminating thread is examined. Results of fault injection experiments on several applications written in C++ and modified to incorporate the object-based checks show that the proposed technique achieves high fault coverage with low performance overhead.

Dual-VDD FPGA architecture has been proposed to reduce the FPGA's power consumption, where a low VDD (VDDL) is assigned to non-critical resources and unused resources are power-gated. In this paper, a path-delay-distribution (PDD) based design method of supply voltage in dual-VDD FPGA is developed, which gives an estimated optimal VDD solution for the required applications. Meanwhile, an improved tree-based VDD assignment algorithm is accordingly designed. Thus chip-level optimization of dual-VDD FPGA is achieved on the chosen granularity with the power consumption minimized. Based on MCNC benchmark circuits at 90nm technology node, our experimental result shows that: the power reduction rate depends on VDDL level; the design method proposed in this work gives the optimal one automatically. This design method could be utilized to guide the FPGA automatic design, saving the time to search for the system's optimal supply voltage, and the proposed assignment algorithm is more efficient in dynamic power reduction.

In this paper, we propose a Multiple Core architecture and an DMA bus connectivity to increase the processing speed of encryption and authentication cores in high speed IPSec security systems. Dynamic partial reconfiguration technology (DPR) is used to reduce FPGA resources and power consumption on chips. This paper proposes a model for high-speed Multiple-IPSec security systems that meet real-time applications. The system throughput, power consumption, and resources used when applying Multiple-Core and DPR architectures are also calculated.

In February 2016, the SuperKEKB positron-electron high-luminosity collider of the KEK laboratory (Tsukuba, Japan) started being commissioned. A dedicated commissioning detector, named BEAST2, has been used to characterize beam backgrounds before the Belle2 detector was rolled into the beams and to provide tuning parameters for Monte Carlo simulations. BEAST2 consists of a fiberglass support structure and several sub-detectors mounted onto it, including time projection chambers (TPCs) and He-3 tubes. In this work, we present direct measurements of radiation-induced single event upsets in a SRAM-based FPGA device installed in BEAST2 at a distance of ∼ 1 m from the beam interaction point. Our goal was to provide experimental results of the expected radiation-induced configuration upset rate and power consumption variation at Belle2 and at other experiments operating in similar radiation environments. Beam currents for both electron and positron rings spanned a range between 50 and 500 mA, therefore providing data about the FPGA operation in different radiation conditions. Even if the machine has not been providing collisions yet, as the beams were not focused to the interaction point, our results show a rate of 0.15 upsets/day averaged over the whole commissioning time frame. We had neither evidence of total dose effects on the FPGA power consumption nor of permanent damage to the device.

Approximate circuit design is an emerging paradigm in which a designer deliberately changes the specified Boolean function to reduce area, delay, and/or power consumption of a circuit. This paper focuses on the synthesis of approximate logic circuits (or ALS) under a given error constraint. In particular, we consider ALS for a two-level design under an error rate constraint. A dynamic programming-based algorithm is proposed to find a nearly optimal approximate function by identifying the most promising set of cubes to be added to the on-set of the original function. Then, an off-the-shelf two-level logic synthesis tool is applied to further optimize the sum-of-product (SOP) expression. The experimental results show that the literal reduction is close to the optimal solution when the error rate constraint is tight and that more than 50% literal reduction is achieved for error rate below 0.8% for an 8-bit adder and a square root circuit.

Both the capacity and the complexity of modern FPGA devices increase rapidly. Also, it is common that battery-powered embedded systems are equipped with FPGA devices. Therefore, reducing the power consumption of FPGA devices has become a very crucial issue. Not only dynamic power consumption but also leakage power consumption increases as the feature size to manufacture FPGA devices shrinks. To reduce the power consumption of FPGA devices, carbon-nanotube field effect transistor (CNFET) has emerged as a promising candidate for replacing silicon metal oxide semiconductor field effect transistor (Si-MOSFET). In this paper, we propose an FPGA slice design based on CNFET technology, and compare the performance and the power consumption characteristics of the proposed design with the same design based on Si-MOSFET. From the performance evaluation, we learned that the proposed design showed up to 5000 times better power-delay product (PDP) than the Si-MOSFET design. Especially reduction in power consumption was truly significant.

With the end of Dennard scaling, FPGA power consumption has become a major concern. While FPGAs are conventionally supplied by a fixed supply voltage (Vdd), recent industrial (SmartVID) and academic solutions (dynamic voltage scaling) have shown significant power savings by scaling the FPGA Vdd on a chip-specific or chip-and application-specific basis. However, FPGAs have historically been designed for fixed-Vdd operation, which raises the question of whether we can design FPGA circuitry that is better suited for voltage scaling. In this work, we show that conventional LUTs are more sensitive to voltage than routing, so we design different LUT circuits that are more tolerant to voltage scaling. Compared to a conventional LUT, our fastest proposed LUT reduces the average critical path delay by 14% and 47% at nominal (0.8 V) Vdd and at reduced (0.6 V) Vdd, respectively. This significant reduction in delay comes at a cost of only 8% FPGA tile area increase. Our proposed LUT designs result in lower energy-delay and energy-delay^2 products at nominal Vdd and below.

The multiply-accumulate unit (MAC) is common in applications like as image and digital signal processing. In order to increase the speed and reduce the power consumption, approximate compressors can be used in the stages of computations. In this paper, three 5:2 approximate compressors are proposed and used in 8-bit MAC implementation. Proposed approximate MAC circuits were synthesized using Synopsys Design Compiler and compared with previous designs that used approximate circuits. Examining the error evaluation parameters including ER , MED and NMED shows that the proposed MUX_C3 design is 6%, 58.8% and 58.7% better than other existing designs, respectively. In performance-error rate compromising (PDP- NMED ), it has been shown that the proposed designs have the least error. To evaluate the quality of the results in image processing applications, the proposed approximate MAC were used in the image multiplication operation in MATLAB software. Measurement of SSIM and PSNR parameters show acceptable results.

The service evolution and the rapid increase in traffic levels fuel the interest toward switching paradigms enabling the fast allocation of Wavelength Division Multiplexing WDM channels in an on demand fashion with fine granularities (microsecond scales). For this reason, in the last years, different optical switching paradigms have been proposed (Sabella et al., 2000): optical-packet switching (OPS), optical-burst switching (OBS), wavelength-routed OBS, etc. Among the various all-optical switching paradigms, OPS attracts increasing attention. Owing to the high switching rate, Semiconductor Optical Amplifier (SOA) is a key technology to realize Optical Packet Switches. We propose some Optical Packet Switch (OPS) architectures and illustrate their realization in SOA technology. The effectiveness of the technology in reducing the power consumption is also analyzed. The chapter is organized in three sections. The main blocks (Switching Fabric, Wavelength Conversion stage, Synchronization stage) of an OPS are illustrated in Section 2 where we also show some examples of realizing wavelength converters and synchronizers in SOA technology. Section 3 introduces SOA-based single-stage and multi-stage switching fabrics. Finally the SOA-based OPS power consumption is investigated in Section 4.

As power consumption in digital systems grows rapidly, energy efficiency has become a crucial concern. To address this, approximate computing was proposed as an innovative paradigm. In this work, we realize an approximate logic synthesis (ALS) toolchain utilizing Boolean matrix factorization algorithm based on error sharping technique (ESBMF) and open-source tools, its basic operation is to generate the corresponding approximation circuit by different input error thresholds. Moreover, we also present an approximate image signal processor (APPROX-ISP). Compared to the original counterpart, APPROX-ISP achieves area benefits of 44.2%, 36.7%, 34.1%, 34.5%, power consumption benefits of 49.9%, 38.6%, 37.1%, 52.2%, and delay benefits of 57.6%, 34.9%, 51.0%, 19.5% using 12-bit Adder, 14-bit Adder, 15-bit Adder and 8-bit Multiplier, respectively. Our experiment demonstrates that there is almost no accuracy degradation in machine learning tasks while using APPROX-ISP.

One of the uses of approximate circuits is machine learning (ML) and with the help of inexact logic minimization as well as through probabilistic pruning, these approximate computing circuits can be implemented. Nowadays, these approximate circuits have been widely explored due to their essential factors such as compact silicon areas well as low power consumption in movable devices. This research work shows how a 4:2 compressor can be designed using inexact logic minimization and thereby reversing a few bits of the output to ensure efficiency as well as accuracy. The average area, propagation delay as well as the average power of the proposed 4:2 compressor is been calculated and are employed in the 8 × 8 and 16x16 Dadda multiplier and truncation and rounding-based scalable approximate multiplier (TOSAM). Using Vivado Design Software Systems in 45nm technology, all the simulations were carried out and the MATLAB tool make use of error analysis to distinguish between precise as well as approximate proposed circuits. This work is mainly concentrated on the design of exact and approximate multipliers and measures the error between them and minimization of this error using the Machine Learning approach and finally validated the results on the Artix-7 FPGA development board of part XCA7CSG324_110t, the partial products which are generated by multipliers are added using 4:2 compressor adder. In the case of digital processing at nano-metric scales, approximate or inexact computing is considered one of the important examples. For computer arithmetic designs, inexact computation plays a significant role, and the new approximate 4:2 compressors are used in a multiplier that is based on TOSAM. These architectures mainly depend on various compression aspects to enable inaccuracy in computing which is described as error rate and is also referred to as normalized error distance which is used to satisfy circuit-based figures of merit, the number of transistors, delay as well as consumption of power. For a Dadda multiplier, four distinct approaches for exploiting the suggested approximation compressors are designed as well as evaluated. The usage of approximate multipliers for image processing, as well as a wide range of simulation results, are presented in this work. When contrasted to an accurate design, the proposed designs achieve a substantial reduction in the number of transistors, power dissipation as well as delay. Furthermore, the presented multiplier models exhibit outstanding image multiplication capabilities in terms of average normalized error distance as well as peak signal-to-noise ratio that is more than 50dB for the analyzed image samples. The proposed ML-based digital system has been developed in Vivado Design Suite and synthesized which is designed using Verilog HDL. Based on obtained results, 17% reduction in power, 21% reduction in latency, and 33% improvement in throughput.