Patterning challenges of EUV lithography for 1X-nm node DRAM and beyond

Extreme ultraviolet (EUV) lithography is crucial to enabling technology scaling in pitch and critical dimension (CD). Currently, one of the key challenges of introducing EUV lithography to high volume manufacturing (HVM) is throughput, which requires high source power and high sensitivity chemically amplified photoresists. Important limiters of high sensitivity chemically amplified resists (CAR) are the effects of photon shot noise and resist blur on the number of photons received and of photoacids generated per feature, especially at the pitches required for 7 nm and 5 nm advanced technology nodes. These stochastic effects are reflected in via structures as hole-to-hole CD variation or local CD uniformity (LCDU). Here, we demonstrate a synergy of film stack deposition, EUV lithography, and plasma etch techniques to improve LCDU, which allows the use of high sensitivity resists required for the introduction of EUV HVM. Thus, to improve LCDU to a level required by 5 nm node and beyond, film stack deposition, EUV lithography, and plasma etch processes were combined and co-optimized to enhance LCDU reduction from synergies. Test wafers were created by depositing a pattern transfer stack on a substrate representative of a 5 nm node target layer. The pattern transfer stack consisted of an atomically smooth adhesion layer and two hardmasks and was deposited using the Lam VECTOR PECVD product family. These layers were designed to mitigate hole roughness, absorb out-of-band radiation, and provide additional outlets for etch to improve LCDU and control hole CD. These wafers were then exposed through an ASML NXE3350B EUV scanner using a variety of advanced positive tone EUV CAR. They were finally etched to the target substrate using Lam Flex dielectric etch and Kiyo conductor etch systems. Metrology methodologies to assess dimensional metrics as well as chip performance and defectivity were investigated to enable repeatable patterning process development. Illumination conditions in EUV lithography were optimized to improve normalized image log slope (NILS), which is expected to reduce shot noise related effects. It can be seen that the EUV imaging contrast improvement can further reduce post-develop LCDU from 4.1 nm to 3.9 nm and from 2.8 nm to 2.6 nm. In parallel, etch processes were developed to further reduce LCDU, to control CD, and to transfer these improvements into the final target substrate. We also demonstrate that increasing post-develop CD through dose adjustment can enhance the LCDU reduction from etch. Similar trends were also observed in different pitches down to 40 nm. The solutions demonstrated here are critical to the introduction of EUV lithography in high volume manufacturing. It can be seen that through a synergistic deposition, lithography, and etch optimization, LCDU at a 40 nm pitch can be improved to 1.6 nm (3-sigma) in a target oxide layer and to 1.4 nm (3-sigma) at the photoresist layer.

Semiconductor scaling is slowing down because of difficulties of device manufacturing below logic 7nm node generation. Various lithography candidates which include ArF immersion with resolution enhancement technology (like Inversed Lithography technology), Extreme Ultra Violet lithography and Nano Imprint lithography are being developed to address the situation. In such advanced lithography, shot counts of mask patterns are estimated to increase explosively in critical layers, and then it is hoped that multi beam mask writer (MBMW) is released to handle them within realistic write time. However, ArF immersion technology with multiple patterning will continue to be a mainstream lithography solution for most of the layers. Then, the shot counts in less critical layers are estimated to be stable because of the limitation of resolution in ArF immersion technology. Therefore, single beam mask writer (SBMW) can play an important role for mask production still, relative to MBMW. Also the demand of SBMW seems actually strong for the logic 7nm node. To realize this, we have developed a new SBMW, EBM-9500 for mask fabrication in this generation. A newly introduced electron beam source enables higher current density of 1200A/cm2. Heating effect correction function has also been newly introduced to satisfy the requirements for both pattern accuracy and throughput. In this paper, we will report the configuration and performance of EBM-9500.

As we presented in the last conference, it is much difficult to get down the k1 limit of EUV lithography compared to that of optical lithography especially recent immersion lithography. Even though current 0.33NA NXE3300 tool has enhanced aberration characteristics and variable illumination mode than its predecessor, ADT and NXE3100, still there are limitations related with resolution capability of EUV lithography. First of all, photon shot noise and immature resist performances play an important role in patterning of very fine patterns. As already known, low sensitivity resists have been widely used to reduce shot noise. However, when considering productivity in EUV lithography, high sensitivity resists are inevitable, so it is necessary to increase image contrast by reducing scanner blur like aberration, M3D, stray light et al. We have investigated the impact of aberration and limitation in illumination pupil fill ratio in EUV. In particular, the aberration sensitivity is different by the illumination conditions, this was intensified when using the particular pupil. Because the lens calibration is conducted with standard illumination condition in NXE3300, it is necessary to consider different aberration sensitivity in accordance with pattern and used pupil condition in EUV lithography. To ensure the process margin of tech node close to limit, a flexpupil with low pupil fill ratio (PFR) than 0.2 were required. Hence in order to avoid through-put loss at this condition, the new concept of the illuminator design is required without light loss. Contamination of collector mirror can affect the patterning also. We will also report about the patterning effect of pupil deformation by degraded collector in low PFR condition.

For the successful implementation of extreme ultraviolet lithography (EUVL) technology for the future semiconductor fabrication process, EUV mask technology is considered to be one of the most critical issues. Since EUV light is strongly absorbed by most materials, reflective optics is applied to all the optical components, including the mask. As a result, the EUV mask structure, based on the mirror-type mask blank, is radically different from that of conventional optical lithography. All the mask components must be prepared with great care to consider the 13.5-nm reflection, which requires nano-scale thin-film technologies. The International Technology Road Map for Semiconductors (ITRS) forecasted that the target technology node for EUVL implementation would be 32 nm and below; today, mask defects are the leading challenge for EUV masks. The reflection of a 13.5-nm wavelength requires a multilayer (ML) structure consisting of many alternating layers of materials having dissimilar EUV optical constants. The Bragg reflection—constructive interference of the partially reflected beam at several interfaces—is the only principle to have EUV reflection, and its efficiency is determined by the structural factor (e.g., the thickness of each layer and their ratios) as well as optical properties (refractive index and extinction coefficient). To produce optical contrast for imaging, the patterns with high EUV absorbance should be formed on the top of this ML mirror. An oblique incident light angle, which is inevitable during image transfer with an EUVL system and causes a shadowing effect, imposes a unique restriction for the EUV mask structure. The ML and absorber specifications are specified in the standard SEMI P38-1103.

In this article we describe a laser plasma source for Extreme Ultraviolet Lithography (EUVL) based on a liquid water jet target. Although jet targets are known for some time now, no attempts have been made to prove the functionality of the target under conditions similar to an EUVL production-line facility, that means illumination with high average power laser systems (in the multi-kW regime) at repetition rates in the kHz region. Such systems are currently under development. We used the MBI-burst laser to simulate these extreme illumination conditions. We examined the hydrodynamic stability of the target as a function of the laser repetition rate at different average laser powers (0.6kW and 5kW per burst). Additionally, the dependence of the conversion efficiency on pulse duration in the range from 30ps to 3ns was investigated. From our results one can conclude parameters for future design of driver lasers for EUVL systems.

For many years, lithographic resolution has been the main obstacle in keeping the pace of transistor densification to meet Moore's Law. For the 32 nm node and beyond, new lithography techniques will be used, including immersion ArF (iArF) lithography and extreme ultraviolet lithography (EUVL). As in the past, these techniques will use new types of photoresists with the capability to print smaller feature widths and pitches. Also, such smaller feature sizes will require thinner layers of photoresists, such as under 100 nm. In previous papers, we focused on ArF and iArF photoresist shrinkage. We evaluated the magnitude of shrinkage for both R&D and mature resists as a function of chemical formulation, lithographic sensitivity, scanning electron microscope (SEM) beam condition, and feature size. Shrinkage results were determined by the well accepted methodology described in ISMI's CD-SEM Unified Specification. A model for resist shrinkage, while derived elsewhere, was presented, that can be used to curve-fit to the shrinkage data resulting from multiple repeated measurements of resist features. Parameters in the curve-fit allow for metrics quantifying total shrinkage, shrinkage rate, and initial critical dimension (CD) before e-beam exposure. With these parameters and exhaustive measurements, a fundamental understanding of the phenomenology of the shrinkage trends was achieved, including how the shrinkage behaves differently for different sized features. This work was extended in yet another paper in which we presented a 1-D model for resist shrinkage that can be used to curve-fit to shrinkage curves. Calibration of parameters to describe the photoresist material and the electron beam were all that were required to fit the model to real shrinkage data, as long as the photoresist was thick enough that the beam could not penetrate the entire layer of resist. In this paper, we extend this work yet again to a 2-D model of a trapezoidal photoresist profile. This model thus allows CD shrinkage in thin photoresist to be solved, which is now of great interest for upcoming realistic lithographic processing. It also allows us to predict the change in resist profile with electron dose and the influence of initial resist profile on shrinkage characteristics. In this work, the results from the previous paper will be shown to be consistent with numerically simulated results, thus lending credibility to these papers' postulations. Also, results from this 2-D profile model can also give clues as to how we might, in the future, model the shrinkage of contour edges of 3-D shapes. With these findings, we can conclude with observations about the readiness of SEM metrology for the challenges of future photoresist measurement, as well as estimate the errors involved in calculating the original CD from the shrinkage trend.

For many years, lithographic resolution has been the main obstacle in allowing the pace of transistor densification to meet Moore's Law. For the 32 nm node and beyond, new lithography techniques will be used, including immersion ArF (iArF) lithography and extreme ultraviolet lithography (EUVL). As in the past, these techniques will use new types of photoresists with the capability to print smaller feature widths and pitches. These smaller feature sizes will also require the use of thinner layers of photoresists, such as under 100 nm. In previous papers, we focused on ArF and iArF photoresist shrinkage. We evaluated the magnitude of shrinkage for both R&D and mature resists as a function of chemical formulation, lithographic sensitivity, scanning electron microscope (SEM) beam condition, and feature size. Shrinkage results were determined by the well accepted methodology described in SEMATECH's CD-SEM Unified Specification . In other associated works, we first developed a 1-D model for resist shrinkage for the bottom linewidth and then a 2-D profile model that accounted for shrinkage of all aspects of a trapezoidal profile along a given linescan. A fundamental understanding of the phenomenology of the shrinkage trends was achieved, including how the shrinkage behaves differently for different sized and shaped features. In the 1-D case, calibration of the parameters to describe the photoresist material and the electron beam was all that was required to fit the models to real shrinkage data, as long as the photoresist was thick enough that the beam could not penetrate the entire layer of resist. The later 2-D model included improvements for solving the CD shrinkage in thin photoresists, which is now of great interest for upcoming realistic lithographic processing to explore the change in resist profile with electron dose and to predict the influence of initial resist profile on shrinkage characteristics. The 2-D model also included shrinkage due to both the primary electron beam directly impacting the profile and backscattered electrons from the electron beam impacting the surrounding substrate. This dose from backscattering was shown to be an important component in the resist shrinkage process, such that at lower beam energies, it dominates linewidth shrinkage. In this work, results from a previous paper will be further explored with numerically simulated results and compared to experimental results to validate the model. With these findings, we can demonstrate the state of readiness of these models for predicting the shrinkage characteristics of photoresist measurements and estimating the errors in calculating the original CD from the shrinkage trend.

It seems like EUV is at the center stage of semiconductor industry nowadays. Several leading companies has already established manufacturing foothold on EUV and add the number of equipment steadily where double-digit number of tools are already operational in their realm. Mostly logic and foundry sectors have moved earlier for EUV high volume manufacturing but memory makers are also following suit. In the presentation, it will be reviewed what specific aspects has differentiated the memory sector from logic and foundry in view of EUV adoption. The value of EUV lithography by comparing that of ArF immersion based multiple patterning techniques will be examined. It will be also touched on the current status and future extendibility of EUV lithography in view of DRAM manufacturing will be briefly addressed also.

For 193-nm lithography, water proves to be a suitable immersion fluid. ArF immersion offers the potential to extend conventional optical lithography to the 45-nm node and potentially to the 32-nm node. Additionally, with existing lenses, the immersion option offers the potential to increase the focus window with 50% and more, depending on actual NA and feature type. In this paper we discuss the results on imaging and overlay obtained with immersion. Using a 0.75 NA ArF projection lens, we have built a proto-type immersion scanner using TWINSCAN technology. First experimental data on imaging demonstrated a large gain of depth of focus (DoF), while maintaining image contrast at high scan speed. For first pilot production with immersion, a 0.85 NA ArF lens will be used. The resolution capabilities of this system will support 65 nm node semiconductor devices with a DOF significantly larger than 0.5 um. Early imaging data of such a system confirms a significant increase in focus window.

The chemical amplification provides high sensitivity of resists for deep-uv and extreme-uv (EUV) lithography. On the other hand, the chemical amplification involves photoacid diffusion that causes contrast degradation of the latent image or, in other words, resist blur. We study the influence of the resist blur in high-numerical aperture ArF immersion lithography by using an interferometric exposure tool. The contrast ratio between the resist latent image and the original aerial image was measured for half pitches from 45 to 80 nm. Acid diffusion length for a high-resolution ArF resist was determined as 11 nm in sigma (26 nm in full width at half maximum) assuming a Gaussian blur kernel. The results revealed that the influence of the resist blur is a significant issue for the 45-nm half-pitch node. The reduction of acid diffusion length is highly desirable. Given the tradeoff between the resist resolution and sensitivity, increasing illumination intensity in exposure tools can be an effective means to overcome the challenge of the resist blur. We also demonstrate resist imaging of 30-nm line-and-space pattern with a high-index fluid. While our focus is on ArF immersion lithography, our findings are also relevant to EUV lithography.

SRAM plays an integral role in the power, performance, and area of a mobile system-on-a-chip. To achieve low power and high density, extreme ultraviolet (EUV) technology is adopted for the 7nm FinFET technology [3-4]. Conventional ArF immersion with a single exposure for an extreme high-resolution patterning shows the limitation of lithographic patterning. Therefore, multi-patterning lithographic technique is applied to support a high-resolution lithography. However, this also includes process variations due to using multi-pattering masks. Alternatively, EUV offers competitive scaling with a single-mask with the benefit of smaller wavelength, which provides smaller process variation with less additional pattering. Figure 11.2.1 shows a 7nm EUV FinFET 6T high-density (HD) SRAM bitcell with an area of 0.026μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The pull-up, pass-gate, and pull-down ratios are 1:1:1 for high-density and low-power applications. Another benefit of EUV technology also features a bi-directional metal layer with a scaled pitch that provides an extra degree of freedom for signal and power routing. Figure 11.2.2 highlights EUV benefits in accordance with bi-directional metals. A uni-directional metal layer requires different metal layer to connect two nets, and have no choice but to support the limited via between two perpendicular metal lines with the limited metal width. A wider metal allows placement of more vias between the metal lines, but it does not demonstrate optimum Power, Performance, and Area (PPA) with redundant parasitic capacitance. However, EUV provides bi-directional metal lines, where the different layers of metal are coherent in the same direction. Therefore, more vias can be placed to reduce the IR-drop with smaller parasitic capacitance and resistance. Figure 11.2.2 illustrates the delay impact versus stacked-via distance in a standard cell array. It shows that the timing penalty is directly proportional to the stacked via distance in a uni-directional metal routing.

The graphoepitaxy DSA process relies on lithographically created confinement wells to perform directed self-assembly in the thin film of the block copolymer. These self-assembled patterns are then etch transferred into the substrate. The conventional DUV immersion or EUV lithography is still required to print these confinement wells, and the lithographic patterning residual errors propagate to the final patterns created by DSA process. DSA proximity correction (PC), in addition to OPC, is essential to obtain accurate confinement well shapes that resolve the final DSA patterns precisely. In this study, we proposed a novel correction flow that integrates our co-optimization algorithms, rigorous 2-D DSA simulation engine, and OPC tool. This flow enables us to optimize our process and integration as well as provides a guidance to design optimization. We also showed that novel RET techniques such as DSA-Aware assist feature generation can be used to improve the process window. The feasibility of our DSA correction framework on large layout with promising correction accuracy has been demonstrated. A robust and efficient correction algorithm is also determined by rigorous verification studies. We also explored how the knowledge of DSA natural pitches and lithography printing constraints provide a good guidance to establish DSA-Friendly designs. Finally application of our DSA full-chip computational correction framework to several real designs of contact-like holes is discussed. We also summarize the challenges associated with computational DSA technology.

Influence of MEEF change on the mask shadowing effect in extreme ultraviolet lithography

Achieving low‐cost patterning of 10 nm‐scale nanostructures remains a critical challenge in nanofabrication. Conventional electron beam lithography has a prolonged processing time and limited throughput due to its intrinsic small‐area processing nature. Extreme ultraviolet (EUV) lithography faces prohibitive costs in equipment and materials. While industrial nanoimprinting offers a lower‐cost, high‐throughput alternative, its resolution is fundamentally constrained by the template's minimum feature size. Herein, we present a new nanofabrication process that exploits the redeposition effect in ion milling to fabricate controllable 10 nm‐scale nanogaps. This approach enabled the preparation of gratings and nanorings array integrated with noble metal nanogaps for applications in surface‐enhanced Raman spectroscopy (SERS). Furthermore, gratings and nanopillar arrays with sidewalls coated by a metal mask were dry‐etched to form a self‐aligned stacked nanomorphology on a silicon substrate without optical alignment, inheriting the metal mask's minimum feature size. The resulting high‐quality templates subsequently facilitated high‐fidelity replication of diminutive structures via nanoimprint lithography (NIL). This scalable strategy holds significant potential as a feasible route for manufacturing applications in nanophononics, biosensing, quantum devices, integrated circuits (ICs), and beyond.

Photomask used for optical lithography has been developed for purpose of fabrication a pattern along with finer designed rules and increase the productivity. With regard to pattern fabrication on mask, EB (Electron beam) mask writer has been used because it has high resolution beam. But in producing photomask, minimum pattern size on mask is hits a peak around 40nm by the resolution limit of ArF immersion systems. This value is easy to achieve by current EB writer. So, photomask process with EB writer has gotten attached to increase turnaround time. In next generation lithography such as EUV (Extreme ultraviolet) lithography and Nano-imprint lithography, it is enable to fabricate finer pattern beyond the resolution limit of ArF immersion systems. Thereby the pattern on a mask becomes finer rapidly. According to ITRS 2012, fabrication of finer patterns less than 20nm will be required on EUV mask and on NIL template. Especially in NIL template, less than 15nm pattern will be required half a decade later. But today’s development of EB writer is aiming to increase photomask’s productivity, so we will face a difficulty to fabricate finer pattern in near future. In this paper, we examined a potential of mask production process with EB writer from the view of finer pattern fabrication performances. We succeeded to fabricate hp (half-pitch) 17nm pattern on mask plate by using VSB (Variable Shaped Beam) type EB mask writer with CAR (Chemically Amplified Resist). This result suggests that the photomask fabrication process has the potential for sub-20nm generation mask production.